353 lines
6.0 KiB
Plaintext
353 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3576.dtsi"
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#include "rk3576-evb1.dtsi"
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#include "rk3576-android.dtsi"
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/ {
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model = "Rockchip RK3576 EVB1 V10 Board + Rockchip NVP6324 AHD to MIPI Extboard";
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compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
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};
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&csi2_dcphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dcphy0_in_n4: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&n4_out0>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidcphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi0_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy0_in_n4: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&n4_out1>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi1_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy3 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy3_in_n4: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&n4_out2>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy3_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi3_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy0_hw {
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status = "okay";
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};
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&csi2_dphy1_hw {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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pinctrl-0 = <&i2c4m3_xfer>;
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jaguar0: jaguar0@30 {
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compatible = "jaguar1-v4l2";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru CLK_MIPI_CAMERAOUT_M0>;
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clock-names = "xvclk";
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clk0m0_clk0>;
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power-domains = <&power RK3576_PD_VI>;
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pd-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //rk3576 evb1 NC as default
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//avdd-supply = <&vcc_mipicsi0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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rockchip,default_rect= <1920 1080>; // default resolution
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port {
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n4_out0: endpoint {
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remote-endpoint = <&mipi_dcphy0_in_n4>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&i2c5 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5m3_xfer>;
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jaguar1: jaguar1@30 {
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compatible = "jaguar1-v4l2";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru CLK_MIPI_CAMERAOUT_M1>;
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clock-names = "xvclk";
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power-domains = <&power RK3576_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clk1m0_clk1>;
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pd-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
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//avdd-supply = <&vcc_mipicsi0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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rockchip,default_rect= <1920 1080>; // default resolution
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port {
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n4_out1: endpoint {
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remote-endpoint = <&mipi_dphy0_in_n4>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&i2c8 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c8m2_xfer>;
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jaguar2: jaguar2@30 {
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compatible = "jaguar1-v4l2";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru CLK_MIPI_CAMERAOUT_M2>;
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clock-names = "xvclk";
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power-domains = <&power RK3576_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clk2m0_clk2>;
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pd-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
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//avdd-supply = <&vcc_mipicsi1>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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rockchip,default_rect= <1920 1080>; // default resolution
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port {
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n4_out2: endpoint {
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remote-endpoint = <&mipi_dphy3_in_n4>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&mipi0_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidcphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in0>;
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};
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};
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};
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};
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&mipi1_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in1>;
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};
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};
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};
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};
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&mipi3_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi3_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy3_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi3_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in3>;
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};
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};
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};
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};
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&rkcif {
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status = "okay";
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rockchip,android-usb-camerahal-enable;
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};
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&rkcif_mipi_lvds {
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status = "okay";
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port {
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cif_mipi_in0: endpoint {
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remote-endpoint = <&mipi0_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds1 {
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status = "okay";
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port {
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cif_mipi_in1: endpoint {
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remote-endpoint = <&mipi1_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds3 {
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status = "okay";
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port {
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cif_mipi_in3: endpoint {
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remote-endpoint = <&mipi3_csi2_output>;
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};
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};
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};
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&rkcif_mmu {
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status = "okay";
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};
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&vcc_mipidcphy0 {
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regulator-boot-on;
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regulator-always-on;
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};
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&vcc_mipicsi0 {
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regulator-boot-on;
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regulator-always-on;
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};
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&vcc_mipicsi1 {
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regulator-boot-on;
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regulator-always-on;
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};
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