165 lines
3.5 KiB
Plaintext
165 lines
3.5 KiB
Plaintext
/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/rockchip,rk3576-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/display/drm_mipi_dsi.h>
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/ {
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compatible = "rockchip,rk3588";
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fragment@0 {
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target = <&dsi>;
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__overlay__ {
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status = "okay";
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dsi_panel: panel@0 {
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status = "okay";
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compatible = "simple-panel-dsi";
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reg = <0>;
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enable-delay-ms = <120>;
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prepare-delay-ms = <120>;
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reset-delay-ms = <120>;
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init-delay-ms = <120>;
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unprepare-delay-ms = <120>;
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disable-delay-ms = <120>;
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size,width = <43>;
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size,height = <57>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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dsi,lanes = <1>;
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panel-init-sequence = [
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39 00 06 FF 77 01 00 00 13
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15 00 02 EF 08
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39 00 06 FF 77 01 00 00 10
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39 00 03 C0 4f 00
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39 00 03 C1 10 0c
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39 00 03 C2 07 14
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15 00 02 CC 10
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39 00 11 B0 00 0B 13 0D 10 07 02 08 07 1F 04 11 0F 28 2F 1F
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39 00 11 B1 00 0C 13 0C 10 05 02 08 08 1E 05 13 11 27 30 1F
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39 00 06 FF 77 01 00 00 11
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15 00 02 B0 4D
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15 00 02 B1 55
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15 00 02 B2 87
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15 00 02 B3 80
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15 00 02 B5 45
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15 00 02 B7 85
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15 00 02 B8 20
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15 00 02 C0 09
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15 00 02 C1 78
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15 00 02 C2 78
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15 00 02 C7 FF
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15 64 02 D0 88
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39 00 04 E0 00 00 02
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39 00 0C E1 06 A0 08 A0 05 A0 07 A0 00 44 44
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39 00 0E E2 20 20 44 44 96 A0 00 00 96 A0 00 00 00
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39 00 05 E3 00 00 22 22
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39 00 03 E4 44 44
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39 00 11 E5 0C 90 B0 A0 0E 92 B0 A0 08 8C B0 A0 0A 8E B0 A0
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39 00 05 E6 00 00 22 22
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39 00 03 E7 44 44
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39 00 11 E8 0C 90 A0 A0 0E 92 A0 A0 08 8C A0 A0 0A 8E A0 A0
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39 00 03 E9 36 00
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39 00 08 EB 00 00 E4 E4 44 88 40
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39 00 11 ED F1 B2 AC 0F 67 45 FF FF FF FF 54 76 F0 CA 2B 1F
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39 00 07 EF 10 0D 04 08 3F 1F
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39 00 06 FF 77 01 00 00 13
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39 00 03 E8 00 0E
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39 00 06 FF 77 01 00 00 11
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39 00 06 FF 77 01 00 00 10
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15 00 02 C7 04
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39 78 06 FF 77 01 00 00 13
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39 00 03 E8 00 0C
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39 0A 03 E8 00 00
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39 78 06 FF 77 01 00 00 00
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15 00 02 36 10
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05 78 01 11
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05 14 01 29
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];
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panel-exit-sequence = [
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05 00 01 28
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05 00 01 10
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];
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disp_timings0: display-timings {
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native-mode = <&dsi1_timing0>;
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dsi1_timing0: timing0 {
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clock-frequency = <25000000>;
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hactive = <480>;
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vactive = <640>;
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hsync-len = <4>;
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hback-porch = <20>;
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hfront-porch = <10>;
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vsync-len = <4>;
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vback-porch = <14>;
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vfront-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <1>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_panel>;
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi_out_panel: endpoint {
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remote-endpoint = <&panel_in_dsi>;
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};
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};
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};
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};
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};
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fragment@1 {
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target = <&mipidcphy0>;
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__overlay__ {
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status = "okay";
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};
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};
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fragment@2 {
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target = <&route_dsi>;
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__overlay__ {
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status = "disabled";
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};
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};
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fragment@3 {
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target = <&dsi_in_vp1>;
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__overlay__ {
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status = "okay";
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};
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};
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fragment@4 {
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target = <&vp1>;
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__overlay__ {
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assigned-clocks = <&cru DCLK_VP1_SRC>;
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assigned-clock-parents = <&cru PLL_VPLL>;
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};
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};
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};
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