/dts-v1/;
/plugin/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/rockchip,rk3576-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/drm_mipi_dsi.h>

/ {
	compatible = "rockchip,rk3588";

	fragment@0 {
		target = <&dsi>;
		__overlay__ {
			status = "okay";
			dsi_panel: panel@0 {
				status = "okay";
				compatible = "simple-panel-dsi";
				reg = <0>;

				enable-delay-ms = <120>;
				prepare-delay-ms = <120>;
				reset-delay-ms = <120>;
				init-delay-ms = <120>;
				unprepare-delay-ms = <120>;
				disable-delay-ms = <120>;

				size,width = <43>;
				size,height = <57>;

				dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
					MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>;
				dsi,format = <MIPI_DSI_FMT_RGB888>;
				dsi,lanes = <1>;

				panel-init-sequence = [
					39 00 06 FF 77 01 00 00 13
					15 00 02 EF 08
					39 00 06 FF 77 01 00 00 10
					39 00 03 C0 4f 00
					39 00 03 C1 10 0c
					39 00 03 C2 07 14
					15 00 02 CC 10
					39 00 11 B0 00 0B 13 0D 10 07 02 08 07 1F 04 11 0F 28 2F 1F
					39 00 11 B1 00 0C 13 0C 10 05 02 08 08 1E 05 13 11 27 30 1F
					39 00 06 FF 77 01 00 00 11
					15 00 02 B0 4D
					15 00 02 B1 55
					15 00 02 B2 87
					15 00 02 B3 80
					15 00 02 B5 45
					15 00 02 B7 85
					15 00 02 B8 20
					15 00 02 C0 09
					15 00 02 C1 78
					15 00 02 C2 78
					15 00 02 C7 FF
					15 64 02 D0 88
					39 00 04 E0 00 00 02
					39 00 0C E1 06 A0 08 A0 05 A0 07 A0 00 44 44
					39 00 0E E2 20 20 44 44 96 A0 00 00 96 A0 00 00 00
					39 00 05 E3 00 00 22 22
					39 00 03 E4 44 44
					39 00 11 E5 0C 90 B0 A0 0E 92 B0 A0 08 8C B0 A0 0A 8E B0 A0
					39 00 05 E6 00 00 22 22
					39 00 03 E7 44 44
					39 00 11 E8 0C 90 A0 A0 0E 92 A0 A0 08 8C A0 A0 0A 8E A0 A0
					39 00 03 E9 36 00
					39 00 08 EB 00 00 E4 E4 44 88 40
					39 00 11 ED F1 B2 AC 0F 67 45 FF FF FF FF 54 76 F0 CA 2B 1F
					39 00 07 EF 10 0D 04 08 3F 1F
					39 00 06 FF 77 01 00 00 13
					39 00 03 E8 00 0E
					39 00 06 FF 77 01 00 00 11
					39 00 06 FF 77 01 00 00 10
					15 00 02 C7 04
					39 78 06 FF 77 01 00 00 13
					39 00 03 E8 00 0C
					39 0A 03 E8 00 00
					39 78 06 FF 77 01 00 00 00
					15 00 02 36 10
					05 78 01 11
					05 14 01 29
				];

				panel-exit-sequence = [
					05 00 01 28
					05 00 01 10
				];

				disp_timings0: display-timings {
					native-mode = <&dsi1_timing0>;
					dsi1_timing0: timing0 {
						clock-frequency = <25000000>;
						hactive = <480>;
						vactive = <640>;
						hsync-len = <4>;
						hback-porch = <20>;
						hfront-porch = <10>;
						vsync-len = <4>;
						vback-porch = <14>;
						vfront-porch = <8>;
						hsync-active = <0>;
						vsync-active = <0>;
						de-active = <0>;
						pixelclk-active = <1>;
					};
				};
				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						panel_in_dsi: endpoint {
							remote-endpoint = <&dsi_out_panel>;
						};
					};
				};
			};
			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					reg = <1>;
					dsi_out_panel: endpoint {
						remote-endpoint = <&panel_in_dsi>;
					};
				};
			};
		};
	};

	fragment@1 {
		target = <&mipidcphy0>;
		__overlay__ {
			status = "okay";
		};
	};

	fragment@2 {
		target = <&route_dsi>;
		__overlay__ {
			status = "disabled";
		};
	};

	fragment@3 {
		target = <&dsi_in_vp1>;
		__overlay__ {
			status = "okay";
		};
	};

	fragment@4 {
		target = <&vp1>;
		__overlay__ {
			assigned-clocks = <&cru DCLK_VP1_SRC>;
			assigned-clock-parents = <&cru PLL_VPLL>;
		};
	};
};