124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <stdio.h>
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#include <stdlib.h>
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#include "util/evsel.h"
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#include "util/env.h"
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#include "util/pmu.h"
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#include "linux/string.h"
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#include "evsel.h"
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#include "util/debug.h"
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#include "env.h"
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#define IBS_FETCH_L3MISSONLY (1ULL << 59)
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#define IBS_OP_L3MISSONLY (1ULL << 16)
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void arch_evsel__set_sample_weight(struct evsel *evsel)
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{
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evsel__set_sample_bit(evsel, WEIGHT_STRUCT);
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}
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void arch_evsel__fixup_new_cycles(struct perf_event_attr *attr)
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{
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struct perf_env env = { .total_mem = 0, } ;
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if (!perf_env__cpuid(&env))
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return;
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/*
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* On AMD, precise cycles event sampling internally uses IBS pmu.
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* But IBS does not have filtering capabilities and perf by default
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* sets exclude_guest = 1. This makes IBS pmu event init fail and
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* thus perf ends up doing non-precise sampling. Avoid it by clearing
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* exclude_guest.
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*/
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if (env.cpuid && strstarts(env.cpuid, "AuthenticAMD"))
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attr->exclude_guest = 0;
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free(env.cpuid);
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}
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/* Check whether the evsel's PMU supports the perf metrics */
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bool evsel__sys_has_perf_metrics(const struct evsel *evsel)
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{
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const char *pmu_name = evsel->pmu_name ? evsel->pmu_name : "cpu";
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/*
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* The PERF_TYPE_RAW type is the core PMU type, e.g., "cpu" PMU
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* on a non-hybrid machine, "cpu_core" PMU on a hybrid machine.
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* The slots event is only available for the core PMU, which
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* supports the perf metrics feature.
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* Checking both the PERF_TYPE_RAW type and the slots event
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* should be good enough to detect the perf metrics feature.
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*/
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if ((evsel->core.attr.type == PERF_TYPE_RAW) &&
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pmu_have_event(pmu_name, "slots"))
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return true;
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return false;
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}
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bool arch_evsel__must_be_in_group(const struct evsel *evsel)
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{
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if (!evsel__sys_has_perf_metrics(evsel))
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return false;
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return evsel->name &&
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(strcasestr(evsel->name, "slots") ||
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strcasestr(evsel->name, "topdown"));
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}
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int arch_evsel__hw_name(struct evsel *evsel, char *bf, size_t size)
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{
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u64 event = evsel->core.attr.config & PERF_HW_EVENT_MASK;
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u64 pmu = evsel->core.attr.config >> PERF_PMU_TYPE_SHIFT;
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const char *event_name;
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if (event < PERF_COUNT_HW_MAX && evsel__hw_names[event])
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event_name = evsel__hw_names[event];
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else
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event_name = "unknown-hardware";
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/* The PMU type is not required for the non-hybrid platform. */
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if (!pmu)
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return scnprintf(bf, size, "%s", event_name);
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return scnprintf(bf, size, "%s/%s/",
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evsel->pmu_name ? evsel->pmu_name : "cpu",
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event_name);
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}
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static void ibs_l3miss_warn(void)
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{
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pr_warning(
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"WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled\n"
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"and tagged operation does not cause L3 Miss. This causes sampling period skew.\n");
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}
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void arch__post_evsel_config(struct evsel *evsel, struct perf_event_attr *attr)
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{
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struct perf_pmu *evsel_pmu, *ibs_fetch_pmu, *ibs_op_pmu;
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static int warned_once;
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if (warned_once || !x86__is_amd_cpu())
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return;
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evsel_pmu = evsel__find_pmu(evsel);
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if (!evsel_pmu)
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return;
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ibs_fetch_pmu = perf_pmu__find("ibs_fetch");
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ibs_op_pmu = perf_pmu__find("ibs_op");
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if (ibs_fetch_pmu && ibs_fetch_pmu->type == evsel_pmu->type) {
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if (attr->config & IBS_FETCH_L3MISSONLY) {
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ibs_l3miss_warn();
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warned_once = 1;
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}
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} else if (ibs_op_pmu && ibs_op_pmu->type == evsel_pmu->type) {
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if (attr->config & IBS_OP_L3MISSONLY) {
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ibs_l3miss_warn();
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warned_once = 1;
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}
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}
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}
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