94 lines
1.7 KiB
C
94 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition
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*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Trevor Wu <trevor.wu@mediatek.com>
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*/
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#ifndef _MT8195_AUDSYS_CLKID_H_
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#define _MT8195_AUDSYS_CLKID_H_
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enum{
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CLK_AUD_AFE,
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CLK_AUD_LRCK_CNT,
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CLK_AUD_SPDIFIN_TUNER_APLL,
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CLK_AUD_SPDIFIN_TUNER_DBG,
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CLK_AUD_UL_TML,
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CLK_AUD_APLL1_TUNER,
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CLK_AUD_APLL2_TUNER,
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CLK_AUD_TOP0_SPDF,
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CLK_AUD_APLL,
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CLK_AUD_APLL2,
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CLK_AUD_DAC,
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CLK_AUD_DAC_PREDIS,
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CLK_AUD_TML,
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CLK_AUD_ADC,
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CLK_AUD_DAC_HIRES,
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CLK_AUD_A1SYS_HP,
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CLK_AUD_AFE_DMIC1,
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CLK_AUD_AFE_DMIC2,
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CLK_AUD_AFE_DMIC3,
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CLK_AUD_AFE_DMIC4,
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CLK_AUD_AFE_26M_DMIC_TM,
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CLK_AUD_UL_TML_HIRES,
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CLK_AUD_ADC_HIRES,
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CLK_AUD_ADDA6_ADC,
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CLK_AUD_ADDA6_ADC_HIRES,
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CLK_AUD_LINEIN_TUNER,
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CLK_AUD_EARC_TUNER,
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CLK_AUD_I2SIN,
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CLK_AUD_TDM_IN,
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CLK_AUD_I2S_OUT,
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CLK_AUD_TDM_OUT,
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CLK_AUD_HDMI_OUT,
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CLK_AUD_ASRC11,
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CLK_AUD_ASRC12,
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CLK_AUD_MULTI_IN,
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CLK_AUD_INTDIR,
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CLK_AUD_A1SYS,
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CLK_AUD_A2SYS,
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CLK_AUD_PCMIF,
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CLK_AUD_A3SYS,
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CLK_AUD_A4SYS,
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CLK_AUD_MEMIF_UL1,
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CLK_AUD_MEMIF_UL2,
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CLK_AUD_MEMIF_UL3,
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CLK_AUD_MEMIF_UL4,
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CLK_AUD_MEMIF_UL5,
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CLK_AUD_MEMIF_UL6,
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CLK_AUD_MEMIF_UL8,
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CLK_AUD_MEMIF_UL9,
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CLK_AUD_MEMIF_UL10,
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CLK_AUD_MEMIF_DL2,
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CLK_AUD_MEMIF_DL3,
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CLK_AUD_MEMIF_DL6,
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CLK_AUD_MEMIF_DL7,
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CLK_AUD_MEMIF_DL8,
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CLK_AUD_MEMIF_DL10,
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CLK_AUD_MEMIF_DL11,
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CLK_AUD_GASRC0,
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CLK_AUD_GASRC1,
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CLK_AUD_GASRC2,
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CLK_AUD_GASRC3,
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CLK_AUD_GASRC4,
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CLK_AUD_GASRC5,
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CLK_AUD_GASRC6,
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CLK_AUD_GASRC7,
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CLK_AUD_GASRC8,
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CLK_AUD_GASRC9,
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CLK_AUD_GASRC10,
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CLK_AUD_GASRC11,
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CLK_AUD_GASRC12,
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CLK_AUD_GASRC13,
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CLK_AUD_GASRC14,
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CLK_AUD_GASRC15,
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CLK_AUD_GASRC16,
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CLK_AUD_GASRC17,
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CLK_AUD_GASRC18,
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CLK_AUD_GASRC19,
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CLK_AUD_NR_CLK,
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};
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#endif
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