605 lines
16 KiB
C
605 lines
16 KiB
C
/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* GK20A does not have dedicated video memory, and to accurately represent this
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* fact Nouveau will not create a RAM device for it. Therefore its instmem
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* implementation must be done directly on top of system memory, while
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* preserving coherency for read and write operations.
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*
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* Instmem can be allocated through two means:
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* 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory
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* pages contiguous to the GPU. This is the preferred way.
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* 2) If no IOMMU unit is probed, the DMA API is used to allocate physically
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* contiguous memory.
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*
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* In both cases CPU read and writes are performed by creating a write-combined
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* mapping. The GPU L2 cache must thus be flushed/invalidated when required. To
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* be conservative we do this every time we acquire or release an instobj, but
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* ideally L2 management should be handled at a higher level.
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*
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* To improve performance, CPU mappings are not removed upon instobj release.
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* Instead they are placed into a LRU list to be recycled when the mapped space
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* goes beyond a certain threshold. At the moment this limit is 1MB.
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*/
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#include "priv.h"
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#include <core/memory.h>
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#include <core/tegra.h>
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#include <subdev/ltc.h>
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#include <subdev/mmu.h>
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struct gk20a_instobj {
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struct nvkm_memory memory;
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struct nvkm_mm_node *mn;
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struct gk20a_instmem *imem;
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/* CPU mapping */
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u32 *vaddr;
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};
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#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory)
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/*
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* Used for objects allocated using the DMA API
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*/
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struct gk20a_instobj_dma {
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struct gk20a_instobj base;
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dma_addr_t handle;
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struct nvkm_mm_node r;
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};
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#define gk20a_instobj_dma(p) \
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container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base)
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/*
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* Used for objects flattened using the IOMMU API
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*/
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struct gk20a_instobj_iommu {
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struct gk20a_instobj base;
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/* to link into gk20a_instmem::vaddr_lru */
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struct list_head vaddr_node;
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/* how many clients are using vaddr? */
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u32 use_cpt;
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/* will point to the higher half of pages */
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dma_addr_t *dma_addrs;
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/* array of base.mem->size pages (+ dma_addr_ts) */
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struct page *pages[];
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};
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#define gk20a_instobj_iommu(p) \
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container_of(gk20a_instobj(p), struct gk20a_instobj_iommu, base)
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struct gk20a_instmem {
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struct nvkm_instmem base;
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/* protects vaddr_* and gk20a_instobj::vaddr* */
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struct mutex lock;
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/* CPU mappings LRU */
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unsigned int vaddr_use;
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unsigned int vaddr_max;
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struct list_head vaddr_lru;
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/* Only used if IOMMU if present */
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struct mutex *mm_mutex;
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struct nvkm_mm *mm;
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struct iommu_domain *domain;
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unsigned long iommu_pgshift;
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u16 iommu_bit;
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/* Only used by DMA API */
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unsigned long attrs;
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};
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#define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base)
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static enum nvkm_memory_target
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gk20a_instobj_target(struct nvkm_memory *memory)
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{
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return NVKM_MEM_TARGET_NCOH;
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}
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static u8
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gk20a_instobj_page(struct nvkm_memory *memory)
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{
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return 12;
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}
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static u64
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gk20a_instobj_addr(struct nvkm_memory *memory)
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{
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return (u64)gk20a_instobj(memory)->mn->offset << 12;
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}
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static u64
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gk20a_instobj_size(struct nvkm_memory *memory)
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{
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return (u64)gk20a_instobj(memory)->mn->length << 12;
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}
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/*
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* Recycle the vaddr of obj. Must be called with gk20a_instmem::lock held.
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*/
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static void
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gk20a_instobj_iommu_recycle_vaddr(struct gk20a_instobj_iommu *obj)
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{
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struct gk20a_instmem *imem = obj->base.imem;
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/* there should not be any user left... */
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WARN_ON(obj->use_cpt);
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list_del(&obj->vaddr_node);
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vunmap(obj->base.vaddr);
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obj->base.vaddr = NULL;
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imem->vaddr_use -= nvkm_memory_size(&obj->base.memory);
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nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use,
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imem->vaddr_max);
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}
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/*
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* Must be called while holding gk20a_instmem::lock
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*/
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static void
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gk20a_instmem_vaddr_gc(struct gk20a_instmem *imem, const u64 size)
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{
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while (imem->vaddr_use + size > imem->vaddr_max) {
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/* no candidate that can be unmapped, abort... */
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if (list_empty(&imem->vaddr_lru))
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break;
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gk20a_instobj_iommu_recycle_vaddr(
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list_first_entry(&imem->vaddr_lru,
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struct gk20a_instobj_iommu, vaddr_node));
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}
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}
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static void __iomem *
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gk20a_instobj_acquire_dma(struct nvkm_memory *memory)
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{
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struct gk20a_instobj *node = gk20a_instobj(memory);
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struct gk20a_instmem *imem = node->imem;
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struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
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nvkm_ltc_flush(ltc);
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return node->vaddr;
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}
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static void __iomem *
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gk20a_instobj_acquire_iommu(struct nvkm_memory *memory)
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{
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struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
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struct gk20a_instmem *imem = node->base.imem;
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struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
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const u64 size = nvkm_memory_size(memory);
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nvkm_ltc_flush(ltc);
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mutex_lock(&imem->lock);
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if (node->base.vaddr) {
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if (!node->use_cpt) {
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/* remove from LRU list since mapping in use again */
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list_del(&node->vaddr_node);
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}
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goto out;
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}
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/* try to free some address space if we reached the limit */
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gk20a_instmem_vaddr_gc(imem, size);
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/* map the pages */
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node->base.vaddr = vmap(node->pages, size >> PAGE_SHIFT, VM_MAP,
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pgprot_writecombine(PAGE_KERNEL));
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if (!node->base.vaddr) {
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nvkm_error(&imem->base.subdev, "cannot map instobj - "
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"this is not going to end well...\n");
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goto out;
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}
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imem->vaddr_use += size;
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nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n",
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imem->vaddr_use, imem->vaddr_max);
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out:
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node->use_cpt++;
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mutex_unlock(&imem->lock);
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return node->base.vaddr;
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}
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static void
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gk20a_instobj_release_dma(struct nvkm_memory *memory)
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{
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struct gk20a_instobj *node = gk20a_instobj(memory);
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struct gk20a_instmem *imem = node->imem;
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struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
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/* in case we got a write-combined mapping */
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wmb();
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nvkm_ltc_invalidate(ltc);
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}
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static void
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gk20a_instobj_release_iommu(struct nvkm_memory *memory)
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{
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struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
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struct gk20a_instmem *imem = node->base.imem;
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struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
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mutex_lock(&imem->lock);
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/* we should at least have one user to release... */
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if (WARN_ON(node->use_cpt == 0))
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goto out;
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/* add unused objs to the LRU list to recycle their mapping */
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if (--node->use_cpt == 0)
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list_add_tail(&node->vaddr_node, &imem->vaddr_lru);
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out:
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mutex_unlock(&imem->lock);
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wmb();
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nvkm_ltc_invalidate(ltc);
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}
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static u32
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gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset)
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{
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struct gk20a_instobj *node = gk20a_instobj(memory);
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return node->vaddr[offset / 4];
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}
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static void
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gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data)
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{
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struct gk20a_instobj *node = gk20a_instobj(memory);
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node->vaddr[offset / 4] = data;
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}
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static int
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gk20a_instobj_map(struct nvkm_memory *memory, u64 offset, struct nvkm_vmm *vmm,
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struct nvkm_vma *vma, void *argv, u32 argc)
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{
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struct gk20a_instobj *node = gk20a_instobj(memory);
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struct nvkm_vmm_map map = {
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.memory = &node->memory,
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.offset = offset,
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.mem = node->mn,
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};
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return nvkm_vmm_map(vmm, vma, argv, argc, &map);
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}
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static void *
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gk20a_instobj_dtor_dma(struct nvkm_memory *memory)
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{
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struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory);
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struct gk20a_instmem *imem = node->base.imem;
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struct device *dev = imem->base.subdev.device->dev;
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if (unlikely(!node->base.vaddr))
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goto out;
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dma_free_attrs(dev, (u64)node->base.mn->length << PAGE_SHIFT,
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node->base.vaddr, node->handle, imem->attrs);
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out:
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return node;
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}
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static void *
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gk20a_instobj_dtor_iommu(struct nvkm_memory *memory)
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{
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struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
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struct gk20a_instmem *imem = node->base.imem;
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struct device *dev = imem->base.subdev.device->dev;
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struct nvkm_mm_node *r = node->base.mn;
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int i;
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if (unlikely(!r))
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goto out;
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mutex_lock(&imem->lock);
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/* vaddr has already been recycled */
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if (node->base.vaddr)
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gk20a_instobj_iommu_recycle_vaddr(node);
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mutex_unlock(&imem->lock);
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/* clear IOMMU bit to unmap pages */
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r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift);
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/* Unmap pages from GPU address space and free them */
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for (i = 0; i < node->base.mn->length; i++) {
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iommu_unmap(imem->domain,
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(r->offset + i) << imem->iommu_pgshift, PAGE_SIZE);
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dma_unmap_page(dev, node->dma_addrs[i], PAGE_SIZE,
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DMA_BIDIRECTIONAL);
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__free_page(node->pages[i]);
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}
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/* Release area from GPU address space */
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mutex_lock(imem->mm_mutex);
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nvkm_mm_free(imem->mm, &r);
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mutex_unlock(imem->mm_mutex);
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out:
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return node;
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}
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static const struct nvkm_memory_func
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gk20a_instobj_func_dma = {
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.dtor = gk20a_instobj_dtor_dma,
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.target = gk20a_instobj_target,
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.page = gk20a_instobj_page,
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.addr = gk20a_instobj_addr,
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.size = gk20a_instobj_size,
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.acquire = gk20a_instobj_acquire_dma,
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.release = gk20a_instobj_release_dma,
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.map = gk20a_instobj_map,
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};
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static const struct nvkm_memory_func
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gk20a_instobj_func_iommu = {
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.dtor = gk20a_instobj_dtor_iommu,
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.target = gk20a_instobj_target,
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.page = gk20a_instobj_page,
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.addr = gk20a_instobj_addr,
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.size = gk20a_instobj_size,
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.acquire = gk20a_instobj_acquire_iommu,
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.release = gk20a_instobj_release_iommu,
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.map = gk20a_instobj_map,
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};
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static const struct nvkm_memory_ptrs
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gk20a_instobj_ptrs = {
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.rd32 = gk20a_instobj_rd32,
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.wr32 = gk20a_instobj_wr32,
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};
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static int
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gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align,
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struct gk20a_instobj **_node)
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{
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struct gk20a_instobj_dma *node;
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struct nvkm_subdev *subdev = &imem->base.subdev;
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struct device *dev = subdev->device->dev;
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if (!(node = kzalloc(sizeof(*node), GFP_KERNEL)))
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return -ENOMEM;
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*_node = &node->base;
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nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory);
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node->base.memory.ptrs = &gk20a_instobj_ptrs;
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node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT,
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&node->handle, GFP_KERNEL,
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imem->attrs);
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if (!node->base.vaddr) {
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nvkm_error(subdev, "cannot allocate DMA memory\n");
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return -ENOMEM;
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}
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/* alignment check */
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if (unlikely(node->handle & (align - 1)))
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nvkm_warn(subdev,
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"memory not aligned as requested: %pad (0x%x)\n",
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&node->handle, align);
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/* present memory for being mapped using small pages */
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node->r.type = 12;
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node->r.offset = node->handle >> 12;
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node->r.length = (npages << PAGE_SHIFT) >> 12;
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node->base.mn = &node->r;
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return 0;
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}
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static int
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gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align,
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struct gk20a_instobj **_node)
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{
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struct gk20a_instobj_iommu *node;
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struct nvkm_subdev *subdev = &imem->base.subdev;
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struct device *dev = subdev->device->dev;
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struct nvkm_mm_node *r;
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int ret;
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int i;
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/*
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* despite their variable size, instmem allocations are small enough
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* (< 1 page) to be handled by kzalloc
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*/
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if (!(node = kzalloc(sizeof(*node) + ((sizeof(node->pages[0]) +
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sizeof(*node->dma_addrs)) * npages), GFP_KERNEL)))
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return -ENOMEM;
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*_node = &node->base;
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node->dma_addrs = (void *)(node->pages + npages);
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nvkm_memory_ctor(&gk20a_instobj_func_iommu, &node->base.memory);
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node->base.memory.ptrs = &gk20a_instobj_ptrs;
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/* Allocate backing memory */
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for (i = 0; i < npages; i++) {
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struct page *p = alloc_page(GFP_KERNEL);
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dma_addr_t dma_adr;
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if (p == NULL) {
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ret = -ENOMEM;
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goto free_pages;
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}
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node->pages[i] = p;
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dma_adr = dma_map_page(dev, p, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(dev, dma_adr)) {
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nvkm_error(subdev, "DMA mapping error!\n");
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ret = -ENOMEM;
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goto free_pages;
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}
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node->dma_addrs[i] = dma_adr;
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}
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mutex_lock(imem->mm_mutex);
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/* Reserve area from GPU address space */
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ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages,
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align >> imem->iommu_pgshift, &r);
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mutex_unlock(imem->mm_mutex);
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if (ret) {
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nvkm_error(subdev, "IOMMU space is full!\n");
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goto free_pages;
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}
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/* Map into GPU address space */
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for (i = 0; i < npages; i++) {
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u32 offset = (r->offset + i) << imem->iommu_pgshift;
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ret = iommu_map(imem->domain, offset, node->dma_addrs[i],
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PAGE_SIZE, IOMMU_READ | IOMMU_WRITE);
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if (ret < 0) {
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nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret);
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while (i-- > 0) {
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offset -= PAGE_SIZE;
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iommu_unmap(imem->domain, offset, PAGE_SIZE);
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}
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goto release_area;
|
|
}
|
|
}
|
|
|
|
/* IOMMU bit tells that an address is to be resolved through the IOMMU */
|
|
r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift);
|
|
|
|
node->base.mn = r;
|
|
return 0;
|
|
|
|
release_area:
|
|
mutex_lock(imem->mm_mutex);
|
|
nvkm_mm_free(imem->mm, &r);
|
|
mutex_unlock(imem->mm_mutex);
|
|
|
|
free_pages:
|
|
for (i = 0; i < npages && node->pages[i] != NULL; i++) {
|
|
dma_addr_t dma_addr = node->dma_addrs[i];
|
|
if (dma_addr)
|
|
dma_unmap_page(dev, dma_addr, PAGE_SIZE,
|
|
DMA_BIDIRECTIONAL);
|
|
__free_page(node->pages[i]);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
|
|
struct nvkm_memory **pmemory)
|
|
{
|
|
struct gk20a_instmem *imem = gk20a_instmem(base);
|
|
struct nvkm_subdev *subdev = &imem->base.subdev;
|
|
struct gk20a_instobj *node = NULL;
|
|
int ret;
|
|
|
|
nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__,
|
|
imem->domain ? "IOMMU" : "DMA", size, align);
|
|
|
|
/* Round size and align to page bounds */
|
|
size = max(roundup(size, PAGE_SIZE), PAGE_SIZE);
|
|
align = max(roundup(align, PAGE_SIZE), PAGE_SIZE);
|
|
|
|
if (imem->domain)
|
|
ret = gk20a_instobj_ctor_iommu(imem, size >> PAGE_SHIFT,
|
|
align, &node);
|
|
else
|
|
ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT,
|
|
align, &node);
|
|
*pmemory = node ? &node->memory : NULL;
|
|
if (ret)
|
|
return ret;
|
|
|
|
node->imem = imem;
|
|
|
|
nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
|
|
size, align, (u64)node->mn->offset << 12);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *
|
|
gk20a_instmem_dtor(struct nvkm_instmem *base)
|
|
{
|
|
struct gk20a_instmem *imem = gk20a_instmem(base);
|
|
|
|
/* perform some sanity checks... */
|
|
if (!list_empty(&imem->vaddr_lru))
|
|
nvkm_warn(&base->subdev, "instobj LRU not empty!\n");
|
|
|
|
if (imem->vaddr_use != 0)
|
|
nvkm_warn(&base->subdev, "instobj vmap area not empty! "
|
|
"0x%x bytes still mapped\n", imem->vaddr_use);
|
|
|
|
return imem;
|
|
}
|
|
|
|
static const struct nvkm_instmem_func
|
|
gk20a_instmem = {
|
|
.dtor = gk20a_instmem_dtor,
|
|
.memory_new = gk20a_instobj_new,
|
|
.zero = false,
|
|
};
|
|
|
|
int
|
|
gk20a_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
|
struct nvkm_instmem **pimem)
|
|
{
|
|
struct nvkm_device_tegra *tdev = device->func->tegra(device);
|
|
struct gk20a_instmem *imem;
|
|
|
|
if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
|
|
return -ENOMEM;
|
|
nvkm_instmem_ctor(&gk20a_instmem, device, type, inst, &imem->base);
|
|
mutex_init(&imem->lock);
|
|
*pimem = &imem->base;
|
|
|
|
/* do not allow more than 1MB of CPU-mapped instmem */
|
|
imem->vaddr_use = 0;
|
|
imem->vaddr_max = 0x100000;
|
|
INIT_LIST_HEAD(&imem->vaddr_lru);
|
|
|
|
if (tdev->iommu.domain) {
|
|
imem->mm_mutex = &tdev->iommu.mutex;
|
|
imem->mm = &tdev->iommu.mm;
|
|
imem->domain = tdev->iommu.domain;
|
|
imem->iommu_pgshift = tdev->iommu.pgshift;
|
|
imem->iommu_bit = tdev->func->iommu_bit;
|
|
|
|
nvkm_info(&imem->base.subdev, "using IOMMU\n");
|
|
} else {
|
|
imem->attrs = DMA_ATTR_WEAK_ORDERING |
|
|
DMA_ATTR_WRITE_COMBINE;
|
|
|
|
nvkm_info(&imem->base.subdev, "using DMA API\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|