673 lines
20 KiB
C
673 lines
20 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#define gf100_ram(p) container_of((p), struct gf100_ram, base)
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#include "ram.h"
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#include "ramfuc.h"
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#include <core/option.h>
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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#include <subdev/bios/rammap.h>
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#include <subdev/bios/timing.h>
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#include <subdev/clk.h>
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#include <subdev/clk/pll.h>
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struct gf100_ramfuc {
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struct ramfuc base;
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struct ramfuc_reg r_0x10fe20;
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struct ramfuc_reg r_0x10fe24;
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struct ramfuc_reg r_0x137320;
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struct ramfuc_reg r_0x137330;
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struct ramfuc_reg r_0x132000;
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struct ramfuc_reg r_0x132004;
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struct ramfuc_reg r_0x132100;
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struct ramfuc_reg r_0x137390;
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struct ramfuc_reg r_0x10f290;
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struct ramfuc_reg r_0x10f294;
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struct ramfuc_reg r_0x10f298;
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struct ramfuc_reg r_0x10f29c;
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struct ramfuc_reg r_0x10f2a0;
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struct ramfuc_reg r_0x10f300;
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struct ramfuc_reg r_0x10f338;
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struct ramfuc_reg r_0x10f340;
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struct ramfuc_reg r_0x10f344;
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struct ramfuc_reg r_0x10f348;
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struct ramfuc_reg r_0x10f910;
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struct ramfuc_reg r_0x10f914;
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struct ramfuc_reg r_0x100b0c;
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struct ramfuc_reg r_0x10f050;
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struct ramfuc_reg r_0x10f090;
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struct ramfuc_reg r_0x10f200;
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struct ramfuc_reg r_0x10f210;
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struct ramfuc_reg r_0x10f310;
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struct ramfuc_reg r_0x10f314;
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struct ramfuc_reg r_0x10f610;
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struct ramfuc_reg r_0x10f614;
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struct ramfuc_reg r_0x10f800;
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struct ramfuc_reg r_0x10f808;
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struct ramfuc_reg r_0x10f824;
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struct ramfuc_reg r_0x10f830;
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struct ramfuc_reg r_0x10f988;
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struct ramfuc_reg r_0x10f98c;
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struct ramfuc_reg r_0x10f990;
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struct ramfuc_reg r_0x10f998;
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struct ramfuc_reg r_0x10f9b0;
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struct ramfuc_reg r_0x10f9b4;
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struct ramfuc_reg r_0x10fb04;
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struct ramfuc_reg r_0x10fb08;
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struct ramfuc_reg r_0x137300;
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struct ramfuc_reg r_0x137310;
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struct ramfuc_reg r_0x137360;
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struct ramfuc_reg r_0x1373ec;
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struct ramfuc_reg r_0x1373f0;
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struct ramfuc_reg r_0x1373f8;
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struct ramfuc_reg r_0x61c140;
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struct ramfuc_reg r_0x611200;
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struct ramfuc_reg r_0x13d8f4;
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};
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struct gf100_ram {
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struct nvkm_ram base;
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struct gf100_ramfuc fuc;
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struct nvbios_pll refpll;
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struct nvbios_pll mempll;
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};
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static void
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gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
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{
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struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);
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struct nvkm_fb *fb = ram->base.fb;
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struct nvkm_device *device = fb->subdev.device;
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u32 part = nvkm_rd32(device, 0x022438), i;
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u32 mask = nvkm_rd32(device, 0x022554);
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u32 addr = 0x110974;
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ram_wr32(fuc, 0x10f910, magic);
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ram_wr32(fuc, 0x10f914, magic);
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for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
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if (mask & (1 << i))
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continue;
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ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
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}
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}
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int
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gf100_ram_calc(struct nvkm_ram *base, u32 freq)
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{
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struct gf100_ram *ram = gf100_ram(base);
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struct gf100_ramfuc *fuc = &ram->fuc;
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struct nvkm_subdev *subdev = &ram->base.fb->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_clk *clk = device->clk;
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struct nvkm_bios *bios = device->bios;
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struct nvbios_ramcfg cfg;
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u8 ver, cnt, len, strap;
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struct {
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u32 data;
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u8 size;
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} rammap, ramcfg, timing;
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int ref, div, out;
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int from, mode;
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int N1, M1, P;
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int ret;
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/* lookup memory config data relevant to the target frequency */
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rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
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&cnt, &ramcfg.size, &cfg);
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if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
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nvkm_error(subdev, "invalid/missing rammap entry\n");
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return -EINVAL;
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}
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/* locate specific data set for the attached memory */
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strap = nvbios_ramcfg_index(subdev);
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if (strap >= cnt) {
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nvkm_error(subdev, "invalid ramcfg strap\n");
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return -EINVAL;
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}
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ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
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if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
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nvkm_error(subdev, "invalid/missing ramcfg entry\n");
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return -EINVAL;
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}
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/* lookup memory timings, if bios says they're present */
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strap = nvbios_rd08(bios, ramcfg.data + 0x01);
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if (strap != 0xff) {
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timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
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&cnt, &len);
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if (!timing.data || ver != 0x10 || timing.size < 0x19) {
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nvkm_error(subdev, "invalid/missing timing entry\n");
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return -EINVAL;
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}
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} else {
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timing.data = 0;
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}
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ret = ram_init(fuc, ram->base.fb);
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if (ret)
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return ret;
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/* determine current mclk configuration */
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from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */
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/* determine target mclk configuration */
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if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
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ref = nvkm_clk_read(clk, nv_clk_src_sppll0);
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else
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ref = nvkm_clk_read(clk, nv_clk_src_sppll1);
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div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
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out = (ref * 2) / (div + 2);
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mode = freq != out;
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ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
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if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {
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ram_nuke(fuc, 0x132000);
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ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
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ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
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}
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if (mode == 1) {
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ram_nuke(fuc, 0x10fe20);
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ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
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ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
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}
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// 0x00020034 // 0x0000000a
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ram_wr32(fuc, 0x132100, 0x00000001);
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if (mode == 1 && from == 0) {
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/* calculate refpll */
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ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk,
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&N1, NULL, &M1, &P);
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if (ret <= 0) {
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nvkm_error(subdev, "unable to calc refpll\n");
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return ret ? ret : -ERANGE;
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}
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ram_wr32(fuc, 0x10fe20, 0x20010000);
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ram_wr32(fuc, 0x137320, 0x00000003);
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ram_wr32(fuc, 0x137330, 0x81200006);
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ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
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ram_wr32(fuc, 0x10fe20, 0x20010001);
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ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
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/* calculate mempll */
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ret = gt215_pll_calc(subdev, &ram->mempll, freq,
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&N1, NULL, &M1, &P);
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if (ret <= 0) {
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nvkm_error(subdev, "unable to calc refpll\n");
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return ret ? ret : -ERANGE;
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}
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ram_wr32(fuc, 0x10fe20, 0x20010005);
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ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
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ram_wr32(fuc, 0x132000, 0x18010101);
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ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
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} else
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if (mode == 0) {
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ram_wr32(fuc, 0x137300, 0x00000003);
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}
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if (from == 0) {
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ram_nuke(fuc, 0x10fb04);
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ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
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ram_nuke(fuc, 0x10fb08);
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ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
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ram_wr32(fuc, 0x10f988, 0x2004ff00);
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ram_wr32(fuc, 0x10f98c, 0x003fc040);
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ram_wr32(fuc, 0x10f990, 0x20012001);
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ram_wr32(fuc, 0x10f998, 0x00011a00);
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ram_wr32(fuc, 0x13d8f4, 0x00000000);
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} else {
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ram_wr32(fuc, 0x10f988, 0x20010000);
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ram_wr32(fuc, 0x10f98c, 0x00000000);
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ram_wr32(fuc, 0x10f990, 0x20012001);
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ram_wr32(fuc, 0x10f998, 0x00010a00);
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}
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if (from == 0) {
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// 0x00020039 // 0x000000ba
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}
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// 0x0002003a // 0x00000002
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ram_wr32(fuc, 0x100b0c, 0x00080012);
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// 0x00030014 // 0x00000000 // 0x02b5f070
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// 0x00030014 // 0x00010000 // 0x02b5f070
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ram_wr32(fuc, 0x611200, 0x00003300);
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// 0x00020034 // 0x0000000a
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// 0x00030020 // 0x00000001 // 0x00000000
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ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
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ram_wr32(fuc, 0x10f210, 0x00000000);
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ram_nsec(fuc, 1000);
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if (mode == 0)
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gf100_ram_train(fuc, 0x000c1001);
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ram_wr32(fuc, 0x10f310, 0x00000001);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f090, 0x00000061);
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ram_wr32(fuc, 0x10f090, 0xc000007f);
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ram_nsec(fuc, 1000);
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if (from == 0) {
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ram_wr32(fuc, 0x10f824, 0x00007fd4);
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} else {
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ram_wr32(fuc, 0x1373ec, 0x00020404);
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}
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if (mode == 0) {
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ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
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ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
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ram_wr32(fuc, 0x10f830, 0x41500010);
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ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
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ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
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ram_wr32(fuc, 0x10f050, 0xff000090);
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ram_wr32(fuc, 0x1373ec, 0x00020f0f);
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ram_wr32(fuc, 0x1373f0, 0x00000003);
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ram_wr32(fuc, 0x137310, 0x81201616);
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ram_wr32(fuc, 0x132100, 0x00000001);
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// 0x00020039 // 0x000000ba
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ram_wr32(fuc, 0x10f830, 0x00300017);
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ram_wr32(fuc, 0x1373f0, 0x00000001);
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ram_wr32(fuc, 0x10f824, 0x00007e77);
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ram_wr32(fuc, 0x132000, 0x18030001);
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ram_wr32(fuc, 0x10f090, 0x4000007e);
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ram_nsec(fuc, 2000);
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ram_wr32(fuc, 0x10f314, 0x00000001);
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ram_wr32(fuc, 0x10f210, 0x80000000);
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ram_wr32(fuc, 0x10f338, 0x00300220);
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ram_wr32(fuc, 0x10f300, 0x0000011d);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f290, 0x02060505);
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ram_wr32(fuc, 0x10f294, 0x34208288);
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ram_wr32(fuc, 0x10f298, 0x44050411);
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ram_wr32(fuc, 0x10f29c, 0x0000114c);
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ram_wr32(fuc, 0x10f2a0, 0x42e10069);
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ram_wr32(fuc, 0x10f614, 0x40044f77);
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ram_wr32(fuc, 0x10f610, 0x40044f77);
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ram_wr32(fuc, 0x10f344, 0x00600009);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f348, 0x00700008);
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ram_wr32(fuc, 0x61c140, 0x19240000);
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ram_wr32(fuc, 0x10f830, 0x00300017);
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gf100_ram_train(fuc, 0x80021001);
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gf100_ram_train(fuc, 0x80081001);
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ram_wr32(fuc, 0x10f340, 0x00500004);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f830, 0x01300017);
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ram_wr32(fuc, 0x10f830, 0x00300017);
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// 0x00030020 // 0x00000000 // 0x00000000
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// 0x00020034 // 0x0000000b
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ram_wr32(fuc, 0x100b0c, 0x00080028);
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ram_wr32(fuc, 0x611200, 0x00003330);
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} else {
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ram_wr32(fuc, 0x10f800, 0x00001800);
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ram_wr32(fuc, 0x13d8f4, 0x00000000);
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ram_wr32(fuc, 0x1373ec, 0x00020404);
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ram_wr32(fuc, 0x1373f0, 0x00000003);
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ram_wr32(fuc, 0x10f830, 0x40700010);
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ram_wr32(fuc, 0x10f830, 0x40500010);
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ram_wr32(fuc, 0x13d8f4, 0x00000000);
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ram_wr32(fuc, 0x1373f8, 0x00000000);
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ram_wr32(fuc, 0x132100, 0x00000101);
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ram_wr32(fuc, 0x137310, 0x89201616);
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ram_wr32(fuc, 0x10f050, 0xff000090);
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ram_wr32(fuc, 0x1373ec, 0x00030404);
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ram_wr32(fuc, 0x1373f0, 0x00000002);
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// 0x00020039 // 0x00000011
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ram_wr32(fuc, 0x132100, 0x00000001);
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ram_wr32(fuc, 0x1373f8, 0x00002000);
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ram_nsec(fuc, 2000);
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ram_wr32(fuc, 0x10f808, 0x7aaa0050);
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ram_wr32(fuc, 0x10f830, 0x00500010);
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ram_wr32(fuc, 0x10f200, 0x00ce1000);
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ram_wr32(fuc, 0x10f090, 0x4000007e);
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ram_nsec(fuc, 2000);
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ram_wr32(fuc, 0x10f314, 0x00000001);
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ram_wr32(fuc, 0x10f210, 0x80000000);
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ram_wr32(fuc, 0x10f338, 0x00300200);
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ram_wr32(fuc, 0x10f300, 0x0000084d);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f290, 0x0b343825);
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ram_wr32(fuc, 0x10f294, 0x3483028e);
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ram_wr32(fuc, 0x10f298, 0x440c0600);
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ram_wr32(fuc, 0x10f29c, 0x0000214c);
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ram_wr32(fuc, 0x10f2a0, 0x42e20069);
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ram_wr32(fuc, 0x10f200, 0x00ce0000);
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ram_wr32(fuc, 0x10f614, 0x60044e77);
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ram_wr32(fuc, 0x10f610, 0x60044e77);
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ram_wr32(fuc, 0x10f340, 0x00500000);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f344, 0x00600228);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f348, 0x00700000);
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ram_wr32(fuc, 0x13d8f4, 0x00000000);
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ram_wr32(fuc, 0x61c140, 0x09a40000);
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gf100_ram_train(fuc, 0x800e1008);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x10f800, 0x00001804);
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// 0x00030020 // 0x00000000 // 0x00000000
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// 0x00020034 // 0x0000000b
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ram_wr32(fuc, 0x13d8f4, 0x00000000);
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ram_wr32(fuc, 0x100b0c, 0x00080028);
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ram_wr32(fuc, 0x611200, 0x00003330);
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ram_nsec(fuc, 100000);
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ram_wr32(fuc, 0x10f9b0, 0x05313f41);
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ram_wr32(fuc, 0x10f9b4, 0x00002f50);
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gf100_ram_train(fuc, 0x010c1001);
|
|
}
|
|
|
|
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
|
|
// 0x00020016 // 0x00000000
|
|
|
|
if (mode == 0)
|
|
ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
gf100_ram_prog(struct nvkm_ram *base)
|
|
{
|
|
struct gf100_ram *ram = gf100_ram(base);
|
|
struct nvkm_device *device = ram->base.fb->subdev.device;
|
|
ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
gf100_ram_tidy(struct nvkm_ram *base)
|
|
{
|
|
struct gf100_ram *ram = gf100_ram(base);
|
|
ram_exec(&ram->fuc, false);
|
|
}
|
|
|
|
int
|
|
gf100_ram_init(struct nvkm_ram *base)
|
|
{
|
|
static const u8 train0[] = {
|
|
0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,
|
|
0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
|
|
};
|
|
static const u32 train1[] = {
|
|
0x00000000, 0xffffffff,
|
|
0x55555555, 0xaaaaaaaa,
|
|
0x33333333, 0xcccccccc,
|
|
0xf0f0f0f0, 0x0f0f0f0f,
|
|
0x00ff00ff, 0xff00ff00,
|
|
0x0000ffff, 0xffff0000,
|
|
};
|
|
struct gf100_ram *ram = gf100_ram(base);
|
|
struct nvkm_device *device = ram->base.fb->subdev.device;
|
|
int i;
|
|
|
|
switch (ram->base.type) {
|
|
case NVKM_RAM_TYPE_GDDR5:
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
/* prepare for ddr link training, and load training patterns */
|
|
for (i = 0; i < 0x30; i++) {
|
|
nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8));
|
|
nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8));
|
|
nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]);
|
|
nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]);
|
|
nvkm_wr32(device, 0x10f918, train1[i % 12]);
|
|
nvkm_wr32(device, 0x10f91c, train1[i % 12]);
|
|
nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]);
|
|
nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]);
|
|
nvkm_wr32(device, 0x10f918, train1[i % 12]);
|
|
nvkm_wr32(device, 0x10f91c, train1[i % 12]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32
|
|
gf100_ram_probe_fbpa_amount(struct nvkm_device *device, int fbpa)
|
|
{
|
|
return nvkm_rd32(device, 0x11020c + (fbpa * 0x1000));
|
|
}
|
|
|
|
u32
|
|
gf100_ram_probe_fbp_amount(const struct nvkm_ram_func *func, u32 fbpao,
|
|
struct nvkm_device *device, int fbp, int *pltcs)
|
|
{
|
|
if (!(fbpao & BIT(fbp))) {
|
|
*pltcs = 1;
|
|
return func->probe_fbpa_amount(device, fbp);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
u32
|
|
gf100_ram_probe_fbp(const struct nvkm_ram_func *func,
|
|
struct nvkm_device *device, int fbp, int *pltcs)
|
|
{
|
|
u32 fbpao = nvkm_rd32(device, 0x022554);
|
|
return func->probe_fbp_amount(func, fbpao, device, fbp, pltcs);
|
|
}
|
|
|
|
int
|
|
gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb,
|
|
struct nvkm_ram *ram)
|
|
{
|
|
struct nvkm_subdev *subdev = &fb->subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
struct nvkm_bios *bios = device->bios;
|
|
const u32 rsvd_head = ( 256 * 1024); /* vga memory */
|
|
const u32 rsvd_tail = (1024 * 1024); /* vbios etc */
|
|
enum nvkm_ram_type type = nvkm_fb_bios_memtype(bios);
|
|
u32 fbps = nvkm_rd32(device, 0x022438);
|
|
u64 total = 0, lcomm = ~0, lower, ubase, usize;
|
|
int ret, fbp, ltcs, ltcn = 0;
|
|
|
|
nvkm_debug(subdev, "%d FBP(s)\n", fbps);
|
|
for (fbp = 0; fbp < fbps; fbp++) {
|
|
u32 size = func->probe_fbp(func, device, fbp, <cs);
|
|
if (size) {
|
|
nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
|
|
fbp, size, ltcs);
|
|
lcomm = min(lcomm, (u64)(size / ltcs) << 20);
|
|
total += (u64) size << 20;
|
|
ltcn += ltcs;
|
|
} else {
|
|
nvkm_debug(subdev, "FBP %d: disabled\n", fbp);
|
|
}
|
|
}
|
|
|
|
lower = lcomm * ltcn;
|
|
ubase = lcomm + func->upper;
|
|
usize = total - lower;
|
|
|
|
nvkm_debug(subdev, "Lower: %4lld MiB @ %010llx\n", lower >> 20, 0ULL);
|
|
nvkm_debug(subdev, "Upper: %4lld MiB @ %010llx\n", usize >> 20, ubase);
|
|
nvkm_debug(subdev, "Total: %4lld MiB\n", total >> 20);
|
|
|
|
ret = nvkm_ram_ctor(func, fb, type, total, ram);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nvkm_mm_fini(&ram->vram);
|
|
|
|
/* Some GPUs are in what's known as a "mixed memory" configuration.
|
|
*
|
|
* This is either where some FBPs have more memory than the others,
|
|
* or where LTCs have been disabled on a FBP.
|
|
*/
|
|
if (lower != total) {
|
|
/* The common memory amount is addressed normally. */
|
|
ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
|
|
rsvd_head >> NVKM_RAM_MM_SHIFT,
|
|
(lower - rsvd_head) >> NVKM_RAM_MM_SHIFT, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* And the rest is much higher in the physical address
|
|
* space, and may not be usable for certain operations.
|
|
*/
|
|
ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_MIXED,
|
|
ubase >> NVKM_RAM_MM_SHIFT,
|
|
(usize - rsvd_tail) >> NVKM_RAM_MM_SHIFT, 1);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
/* GPUs without mixed-memory are a lot nicer... */
|
|
ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,
|
|
rsvd_head >> NVKM_RAM_MM_SHIFT,
|
|
(total - rsvd_head - rsvd_tail) >>
|
|
NVKM_RAM_MM_SHIFT, 1);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
gf100_ram_new_(const struct nvkm_ram_func *func,
|
|
struct nvkm_fb *fb, struct nvkm_ram **pram)
|
|
{
|
|
struct nvkm_subdev *subdev = &fb->subdev;
|
|
struct nvkm_bios *bios = subdev->device->bios;
|
|
struct gf100_ram *ram;
|
|
int ret;
|
|
|
|
if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
|
|
return -ENOMEM;
|
|
*pram = &ram->base;
|
|
|
|
ret = gf100_ram_ctor(func, fb, &ram->base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll);
|
|
if (ret) {
|
|
nvkm_error(subdev, "mclk refpll data not found\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = nvbios_pll_parse(bios, 0x04, &ram->mempll);
|
|
if (ret) {
|
|
nvkm_error(subdev, "mclk pll data not found\n");
|
|
return ret;
|
|
}
|
|
|
|
ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20);
|
|
ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24);
|
|
ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
|
|
ram->fuc.r_0x137330 = ramfuc_reg(0x137330);
|
|
|
|
ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
|
|
ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
|
|
ram->fuc.r_0x132100 = ramfuc_reg(0x132100);
|
|
|
|
ram->fuc.r_0x137390 = ramfuc_reg(0x137390);
|
|
|
|
ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
|
|
ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
|
|
ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
|
|
ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
|
|
ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
|
|
|
|
ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);
|
|
ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);
|
|
ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);
|
|
ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344);
|
|
ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348);
|
|
|
|
ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
|
|
ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
|
|
|
|
ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c);
|
|
ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050);
|
|
ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
|
|
ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
|
|
ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
|
|
ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
|
|
ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
|
|
ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
|
|
ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
|
|
ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
|
|
ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
|
|
ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
|
|
ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
|
|
ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988);
|
|
ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c);
|
|
ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990);
|
|
ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998);
|
|
ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0);
|
|
ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4);
|
|
ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04);
|
|
ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08);
|
|
ram->fuc.r_0x137310 = ramfuc_reg(0x137300);
|
|
ram->fuc.r_0x137310 = ramfuc_reg(0x137310);
|
|
ram->fuc.r_0x137360 = ramfuc_reg(0x137360);
|
|
ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
|
|
ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
|
|
ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8);
|
|
|
|
ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140);
|
|
ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
|
|
|
|
ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4);
|
|
return 0;
|
|
}
|
|
|
|
static const struct nvkm_ram_func
|
|
gf100_ram = {
|
|
.upper = 0x0200000000ULL,
|
|
.probe_fbp = gf100_ram_probe_fbp,
|
|
.probe_fbp_amount = gf100_ram_probe_fbp_amount,
|
|
.probe_fbpa_amount = gf100_ram_probe_fbpa_amount,
|
|
.init = gf100_ram_init,
|
|
.calc = gf100_ram_calc,
|
|
.prog = gf100_ram_prog,
|
|
.tidy = gf100_ram_tidy,
|
|
};
|
|
|
|
int
|
|
gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
|
|
{
|
|
return gf100_ram_new_(&gf100_ram, fb, pram);
|
|
}
|