667 lines
18 KiB
C
667 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <drm/drm_crtc.h>
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#include <drm/drm_flip_work.h>
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#include <drm/drm_mode.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include "mdp4_kms.h"
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#include "msm_gem.h"
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struct mdp4_crtc {
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struct drm_crtc base;
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char name[8];
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int id;
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int ovlp;
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enum mdp4_dma dma;
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bool enabled;
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/* which mixer/encoder we route output to: */
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int mixer;
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struct {
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spinlock_t lock;
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bool stale;
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uint32_t width, height;
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uint32_t x, y;
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/* next cursor to scan-out: */
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uint32_t next_iova;
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struct drm_gem_object *next_bo;
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/* current cursor being scanned out: */
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struct drm_gem_object *scanout_bo;
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} cursor;
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/* if there is a pending flip, these will be non-null: */
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struct drm_pending_vblank_event *event;
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/* Bits have been flushed at the last commit,
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* used to decide if a vsync has happened since last commit.
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*/
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u32 flushed_mask;
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#define PENDING_CURSOR 0x1
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#define PENDING_FLIP 0x2
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atomic_t pending;
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/* for unref'ing cursor bo's after scanout completes: */
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struct drm_flip_work unref_cursor_work;
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struct mdp_irq vblank;
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struct mdp_irq err;
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};
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#define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
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static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
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{
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struct msm_drm_private *priv = crtc->dev->dev_private;
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return to_mdp4_kms(to_mdp_kms(priv->kms));
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}
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static void request_pending(struct drm_crtc *crtc, uint32_t pending)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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atomic_or(pending, &mdp4_crtc->pending);
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mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
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}
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static void crtc_flush(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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struct drm_plane *plane;
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uint32_t flush = 0;
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
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flush |= pipe2flush(pipe_id);
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}
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flush |= ovlp2flush(mdp4_crtc->ovlp);
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DBG("%s: flush=%08x", mdp4_crtc->name, flush);
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mdp4_crtc->flushed_mask = flush;
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mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
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}
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/* if file!=NULL, this is preclose potential cancel-flip path */
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static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_pending_vblank_event *event;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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event = mdp4_crtc->event;
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if (event) {
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mdp4_crtc->event = NULL;
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DBG("%s: send event: %p", mdp4_crtc->name, event);
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drm_crtc_send_vblank_event(crtc, event);
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static void unref_cursor_worker(struct drm_flip_work *work, void *val)
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{
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struct mdp4_crtc *mdp4_crtc =
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container_of(work, struct mdp4_crtc, unref_cursor_work);
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struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
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struct msm_kms *kms = &mdp4_kms->base.base;
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msm_gem_unpin_iova(val, kms->aspace);
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drm_gem_object_put(val);
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}
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static void mdp4_crtc_destroy(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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drm_crtc_cleanup(crtc);
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drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
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kfree(mdp4_crtc);
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}
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/* statically (for now) map planes to mixer stage (z-order): */
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static const int idxs[] = {
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[VG1] = 1,
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[VG2] = 2,
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[RGB1] = 0,
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[RGB2] = 0,
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[RGB3] = 0,
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[VG3] = 3,
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[VG4] = 4,
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};
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/* setup mixer config, for which we need to consider all crtc's and
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* the planes attached to them
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*
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* TODO may possibly need some extra locking here
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*/
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static void setup_mixer(struct mdp4_kms *mdp4_kms)
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{
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struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
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struct drm_crtc *crtc;
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uint32_t mixer_cfg = 0;
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static const enum mdp_mixer_stage_id stages[] = {
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STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
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};
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list_for_each_entry(crtc, &config->crtc_list, head) {
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct drm_plane *plane;
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
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int idx = idxs[pipe_id];
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mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
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pipe_id, stages[idx]);
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}
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}
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mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
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}
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static void blend_setup(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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struct drm_plane *plane;
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int i, ovlp = mdp4_crtc->ovlp;
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bool alpha[4]= { false, false, false, false };
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
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int idx = idxs[pipe_id];
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if (idx > 0) {
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const struct mdp_format *format =
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to_mdp_format(msm_framebuffer_format(plane->state->fb));
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alpha[idx-1] = format->alpha_enable;
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}
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}
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for (i = 0; i < 4; i++) {
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uint32_t op;
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if (alpha[i]) {
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op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
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MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
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MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
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} else {
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op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
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MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
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}
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
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}
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setup_mixer(mdp4_kms);
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}
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static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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enum mdp4_dma dma = mdp4_crtc->dma;
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int ovlp = mdp4_crtc->ovlp;
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struct drm_display_mode *mode;
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if (WARN_ON(!crtc->state))
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return;
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mode = &crtc->state->adjusted_mode;
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DBG("%s: set mode: " DRM_MODE_FMT,
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mdp4_crtc->name, DRM_MODE_ARG(mode));
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mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
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MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
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MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
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/* take data from pipe: */
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mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
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MDP4_DMA_DST_SIZE_WIDTH(0) |
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MDP4_DMA_DST_SIZE_HEIGHT(0));
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
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MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
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MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
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if (dma == DMA_E) {
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mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
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}
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}
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static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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unsigned long flags;
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DBG("%s", mdp4_crtc->name);
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if (WARN_ON(!mdp4_crtc->enabled))
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return;
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/* Disable/save vblank irq handling before power is disabled */
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drm_crtc_vblank_off(crtc);
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mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
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mdp4_disable(mdp4_kms);
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if (crtc->state->event && !crtc->state->active) {
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WARN_ON(mdp4_crtc->event);
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spin_lock_irqsave(&mdp4_kms->dev->event_lock, flags);
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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crtc->state->event = NULL;
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spin_unlock_irqrestore(&mdp4_kms->dev->event_lock, flags);
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}
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mdp4_crtc->enabled = false;
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}
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static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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DBG("%s", mdp4_crtc->name);
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if (WARN_ON(mdp4_crtc->enabled))
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return;
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mdp4_enable(mdp4_kms);
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/* Restore vblank irq handling after power is enabled */
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drm_crtc_vblank_on(crtc);
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mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
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crtc_flush(crtc);
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mdp4_crtc->enabled = true;
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}
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static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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DBG("%s: check", mdp4_crtc->name);
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// TODO anything else to check?
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return 0;
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}
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static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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DBG("%s: begin", mdp4_crtc->name);
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}
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static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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unsigned long flags;
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DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
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WARN_ON(mdp4_crtc->event);
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spin_lock_irqsave(&dev->event_lock, flags);
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mdp4_crtc->event = crtc->state->event;
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crtc->state->event = NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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blend_setup(crtc);
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crtc_flush(crtc);
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request_pending(crtc, PENDING_FLIP);
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}
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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/* called from IRQ to update cursor related registers (if needed). The
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* cursor registers, other than x/y position, appear not to be double
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* buffered, and changing them other than from vblank seems to trigger
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* underflow.
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*/
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static void update_cursor(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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struct msm_kms *kms = &mdp4_kms->base.base;
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enum mdp4_dma dma = mdp4_crtc->dma;
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unsigned long flags;
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spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
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if (mdp4_crtc->cursor.stale) {
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struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
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struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
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uint64_t iova = mdp4_crtc->cursor.next_iova;
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if (next_bo) {
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/* take a obj ref + iova ref when we start scanning out: */
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drm_gem_object_get(next_bo);
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msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova);
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/* enable cursor: */
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mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
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MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
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MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
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mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
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MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
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MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
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} else {
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/* disable cursor: */
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mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
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mdp4_kms->blank_cursor_iova);
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}
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/* and drop the iova ref + obj rev when done scanning out: */
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if (prev_bo)
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drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
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mdp4_crtc->cursor.scanout_bo = next_bo;
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mdp4_crtc->cursor.stale = false;
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}
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mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
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MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
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MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
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spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
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}
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static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
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struct drm_file *file_priv, uint32_t handle,
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uint32_t width, uint32_t height)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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struct msm_kms *kms = &mdp4_kms->base.base;
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struct drm_device *dev = crtc->dev;
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struct drm_gem_object *cursor_bo, *old_bo;
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unsigned long flags;
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uint64_t iova;
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int ret;
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if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
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DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
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return -EINVAL;
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}
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if (handle) {
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cursor_bo = drm_gem_object_lookup(file_priv, handle);
|
|
if (!cursor_bo)
|
|
return -ENOENT;
|
|
} else {
|
|
cursor_bo = NULL;
|
|
}
|
|
|
|
if (cursor_bo) {
|
|
ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova);
|
|
if (ret)
|
|
goto fail;
|
|
} else {
|
|
iova = 0;
|
|
}
|
|
|
|
spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
|
|
old_bo = mdp4_crtc->cursor.next_bo;
|
|
mdp4_crtc->cursor.next_bo = cursor_bo;
|
|
mdp4_crtc->cursor.next_iova = iova;
|
|
mdp4_crtc->cursor.width = width;
|
|
mdp4_crtc->cursor.height = height;
|
|
mdp4_crtc->cursor.stale = true;
|
|
spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
|
|
|
|
if (old_bo) {
|
|
/* drop our previous reference: */
|
|
drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
|
|
}
|
|
|
|
request_pending(crtc, PENDING_CURSOR);
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
drm_gem_object_put(cursor_bo);
|
|
return ret;
|
|
}
|
|
|
|
static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
|
|
mdp4_crtc->cursor.x = x;
|
|
mdp4_crtc->cursor.y = y;
|
|
spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
|
|
|
|
crtc_flush(crtc);
|
|
request_pending(crtc, PENDING_CURSOR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_crtc_funcs mdp4_crtc_funcs = {
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.destroy = mdp4_crtc_destroy,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.cursor_set = mdp4_crtc_cursor_set,
|
|
.cursor_move = mdp4_crtc_cursor_move,
|
|
.reset = drm_atomic_helper_crtc_reset,
|
|
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
|
.enable_vblank = msm_crtc_enable_vblank,
|
|
.disable_vblank = msm_crtc_disable_vblank,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
|
|
.mode_set_nofb = mdp4_crtc_mode_set_nofb,
|
|
.atomic_check = mdp4_crtc_atomic_check,
|
|
.atomic_begin = mdp4_crtc_atomic_begin,
|
|
.atomic_flush = mdp4_crtc_atomic_flush,
|
|
.atomic_enable = mdp4_crtc_atomic_enable,
|
|
.atomic_disable = mdp4_crtc_atomic_disable,
|
|
};
|
|
|
|
static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
|
|
struct drm_crtc *crtc = &mdp4_crtc->base;
|
|
struct msm_drm_private *priv = crtc->dev->dev_private;
|
|
unsigned pending;
|
|
|
|
mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
|
|
|
|
pending = atomic_xchg(&mdp4_crtc->pending, 0);
|
|
|
|
if (pending & PENDING_FLIP) {
|
|
complete_flip(crtc, NULL);
|
|
}
|
|
|
|
if (pending & PENDING_CURSOR) {
|
|
update_cursor(crtc);
|
|
drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
|
|
}
|
|
}
|
|
|
|
static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
|
|
struct drm_crtc *crtc = &mdp4_crtc->base;
|
|
DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
|
|
crtc_flush(crtc);
|
|
}
|
|
|
|
static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
int ret;
|
|
|
|
ret = drm_crtc_vblank_get(crtc);
|
|
if (ret)
|
|
return;
|
|
|
|
ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
|
|
!(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
|
|
mdp4_crtc->flushed_mask),
|
|
msecs_to_jiffies(50));
|
|
if (ret <= 0)
|
|
dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
|
|
|
|
mdp4_crtc->flushed_mask = 0;
|
|
|
|
drm_crtc_vblank_put(crtc);
|
|
}
|
|
|
|
uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
return mdp4_crtc->vblank.irqmask;
|
|
}
|
|
|
|
/* set dma config, ie. the format the encoder wants. */
|
|
void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
|
|
}
|
|
|
|
/* set interface for routing crtc->encoder: */
|
|
void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
uint32_t intf_sel;
|
|
|
|
intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
|
|
|
|
switch (mdp4_crtc->dma) {
|
|
case DMA_P:
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
|
|
break;
|
|
case DMA_S:
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
|
|
break;
|
|
case DMA_E:
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
|
|
break;
|
|
}
|
|
|
|
if (intf == INTF_DSI_VIDEO) {
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
|
|
} else if (intf == INTF_DSI_CMD) {
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
|
|
}
|
|
|
|
mdp4_crtc->mixer = mixer;
|
|
|
|
blend_setup(crtc);
|
|
|
|
DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
|
|
|
|
mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
|
|
}
|
|
|
|
void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
|
|
{
|
|
/* wait_for_flush_done is the only case for now.
|
|
* Later we will have command mode CRTC to wait for
|
|
* other event.
|
|
*/
|
|
mdp4_crtc_wait_for_flush_done(crtc);
|
|
}
|
|
|
|
static const char *dma_names[] = {
|
|
"DMA_P", "DMA_S", "DMA_E",
|
|
};
|
|
|
|
/* initialize crtc */
|
|
struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
|
|
struct drm_plane *plane, int id, int ovlp_id,
|
|
enum mdp4_dma dma_id)
|
|
{
|
|
struct drm_crtc *crtc = NULL;
|
|
struct mdp4_crtc *mdp4_crtc;
|
|
|
|
mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
|
|
if (!mdp4_crtc)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
crtc = &mdp4_crtc->base;
|
|
|
|
mdp4_crtc->id = id;
|
|
|
|
mdp4_crtc->ovlp = ovlp_id;
|
|
mdp4_crtc->dma = dma_id;
|
|
|
|
mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
|
|
mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
|
|
|
|
mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
|
|
mdp4_crtc->err.irq = mdp4_crtc_err_irq;
|
|
|
|
snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
|
|
dma_names[dma_id], ovlp_id);
|
|
|
|
spin_lock_init(&mdp4_crtc->cursor.lock);
|
|
|
|
drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
|
|
"unref cursor", unref_cursor_worker);
|
|
|
|
drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
|
|
NULL);
|
|
drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
|
|
|
|
return crtc;
|
|
}
|