92 lines
		
	
	
		
			3.1 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			92 lines
		
	
	
		
			3.1 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| TI SysCon Reset Controller
 | |
| =======================
 | |
| 
 | |
| Almost all SoCs have hardware modules that require reset control in addition
 | |
| to clock and power control for their functionality. The reset control is
 | |
| typically provided by means of memory-mapped I/O registers. These registers are
 | |
| sometimes a part of a larger register space region implementing various
 | |
| functionalities. This register range is best represented as a syscon node to
 | |
| allow multiple entities to access their relevant registers in the common
 | |
| register space.
 | |
| 
 | |
| A SysCon Reset Controller node defines a device that uses a syscon node
 | |
| and provides reset management functionality for various hardware modules
 | |
| present on the SoC.
 | |
| 
 | |
| SysCon Reset Controller Node
 | |
| ============================
 | |
| Each of the reset provider/controller nodes should be a child of a syscon
 | |
| node and have the following properties.
 | |
| 
 | |
| Required properties:
 | |
| --------------------
 | |
|  - compatible		: Should be,
 | |
| 			    "ti,k2e-pscrst"
 | |
| 			    "ti,k2l-pscrst"
 | |
| 			    "ti,k2hk-pscrst"
 | |
| 			    "ti,syscon-reset"
 | |
|  - #reset-cells		: Should be 1. Please see the reset consumer node below
 | |
| 			  for usage details
 | |
|  - ti,reset-bits	: Contains the reset control register information
 | |
| 			  Should contain 7 cells for each reset exposed to
 | |
| 			  consumers, defined as:
 | |
| 			    Cell #1 : offset of the reset assert control
 | |
| 			              register from the syscon register base
 | |
| 			    Cell #2 : bit position of the reset in the reset
 | |
| 			              assert control register
 | |
| 			    Cell #3 : offset of the reset deassert control
 | |
| 			              register from the syscon register base
 | |
| 			    Cell #4 : bit position of the reset in the reset
 | |
| 			              deassert control register
 | |
| 			    Cell #5 : offset of the reset status register
 | |
| 			              from the syscon register base
 | |
| 			    Cell #6 : bit position of the reset in the
 | |
| 			              reset status register
 | |
| 			    Cell #7 : Flags used to control reset behavior,
 | |
| 			              availible flags defined in the DT include
 | |
| 			              file <dt-bindings/reset/ti-syscon.h>
 | |
| 
 | |
| SysCon Reset Consumer Nodes
 | |
| ===========================
 | |
| Each of the reset consumer nodes should have the following properties,
 | |
| in addition to their own properties.
 | |
| 
 | |
| Required properties:
 | |
| --------------------
 | |
|  - resets	: A phandle to the reset controller node and an index number
 | |
| 		  to a reset specifier as defined above.
 | |
| 
 | |
| Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
 | |
| common reset controller usage by consumers.
 | |
| 
 | |
| Example:
 | |
| --------
 | |
| The following example demonstrates a syscon node, the reset controller node
 | |
| using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
 | |
| 66AK2E SoC.
 | |
| 
 | |
| / {
 | |
| 	soc {
 | |
| 		psc: power-sleep-controller@2350000 {
 | |
| 			compatible = "syscon", "simple-mfd";
 | |
| 			reg = <0x02350000 0x1000>;
 | |
| 
 | |
| 			pscrst: reset-controller {
 | |
| 				compatible = "ti,k2e-pscrst", "ti,syscon-reset";
 | |
| 				#reset-cells = <1>;
 | |
| 
 | |
| 				ti,reset-bits = <
 | |
| 					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET   | STATUS_CLEAR) /* 0: dsp0 */
 | |
| 					0xa40 5 0xa44 3 0     0 (ASSERT_SET   | DEASSERT_CLEAR | STATUS_NONE)  /* 1: example */
 | |
| 				>;
 | |
| 			};
 | |
| 		};
 | |
| 
 | |
| 		dsp0: dsp0 {
 | |
| 			...
 | |
| 			resets = <&pscrst 0>;
 | |
| 			...
 | |
| 		};
 | |
| 	};
 | |
| };
 |