681 lines
15 KiB
C
681 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* drivers/soc/rockchip/rockchip_debug.c
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*
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* Arm debug driver
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*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd.
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*/
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/* RK3399
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* debug {
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* compatible = "rockchip,debug";
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* reg = <0x0 0xfe430000 0x0 0x1000>,
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* <0x0 0xfe432000 0x0 0x1000>,
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* <0x0 0xfe434000 0x0 0x1000>,
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* <0x0 0xfe436000 0x0 0x1000>,
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* <0x0 0xfe610000 0x0 0x1000>,
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* <0x0 0xfe710000 0x0 0x1000>;
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* };
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*/
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/* RK3326
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* debug {
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* compatible = "rockchip,debug";
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* reg = <0x0 0xff690000 0x0 0x1000>,
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* <0x0 0xff692000 0x0 0x1000>,
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* <0x0 0xff694000 0x0 0x1000>,
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* <0x0 0xff696000 0x0 0x1000>;
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* };
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*/
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/* RK3308
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* debug {
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* compatible = "rockchip,debug";
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* reg = <0x0 0xff810000 0x0 0x1000>,
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* <0x0 0xff812000 0x0 0x1000>,
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* <0x0 0xff814000 0x0 0x1000>,
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* <0x0 0xff816000 0x0 0x1000>;
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* };
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*/
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/* RK3288
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* debug {
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* compatible = "rockchip,debug";
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* reg = <0x0 0xffbb0000 0x0 0x1000>,
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* <0x0 0xffbb2000 0x0 0x1000>,
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* <0x0 0xffbb4000 0x0 0x1000>,
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* <0x0 0xffbb6000 0x0 0x1000>;
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* };
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/panic_notifier.h>
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#include <linux/kernel_stat.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#if IS_ENABLED(CONFIG_ROCKCHIP_MINIDUMP)
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#include <soc/rockchip/rk_minidump.h>
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#endif
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#include "fiq_debugger/fiq_debugger_priv.h"
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#include "rockchip_debug.h"
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#define EDPCSR_LO 0x0a0
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#define EDPCSR_HI 0x0ac
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#define EDLAR 0xfb0
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#define EDLAR_UNLOCK 0xc5acce55
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#define EDPRSR 0x314
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#define EDPRSR_PU 0x1
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#define EDDEVID 0xFC8
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#define PMPCSR_LO 0x200
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#define PMPCSR_HI 0x204
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#define NUM_CPU_SAMPLES 100
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#define NUM_SAMPLES_TO_PRINT 32
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static void __iomem *rockchip_cpu_debug[16];
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static void __iomem *rockchip_cs_pmu[16];
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static bool edpcsr_present;
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static char log_buf[1024];
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extern struct atomic_notifier_head hardlock_notifier_list;
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extern struct atomic_notifier_head rcu_stall_notifier_list;
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static inline void rockchip_debug_serror_enable(void)
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{
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#ifdef CONFIG_ARM64
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/* enable SError */
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asm volatile("msr daifclr, #0x4");
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#endif
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}
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static inline void rockchip_debug_serror_disable(void)
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{
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#ifdef CONFIG_ARM64
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/* disable SError */
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asm volatile("msr daifset, #0x4");
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#endif
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}
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#if IS_ENABLED(CONFIG_FIQ_DEBUGGER)
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static int rockchip_debug_dump_edpcsr(struct fiq_debugger_output *output)
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{
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unsigned long edpcsr;
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int i = 0, j = 0;
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void *pc = NULL;
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void *prev_pc = NULL;
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int printed = 0;
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void __iomem *base;
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u32 pu = 0, online = 0;
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rockchip_debug_serror_disable();
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while (rockchip_cpu_debug[i]) {
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online = cpu_online(i);
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output->printf(output,
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"CPU%d online:%d\n", i, online);
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if (online == 0) {
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i++;
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continue;
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}
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base = rockchip_cpu_debug[i];
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pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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output->printf(output,
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"CPU%d power down\n", i);
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i++;
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continue;
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}
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/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
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writel(EDLAR_UNLOCK, base + EDLAR);
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/* Try to read a bunch of times if CPU is actually running */
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for (j = 0; j < NUM_CPU_SAMPLES &&
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printed < NUM_SAMPLES_TO_PRINT; j++) {
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pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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output->printf(output,
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"CPU%d power down\n", i);
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break;
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}
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if (sizeof(edpcsr) == 8)
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edpcsr = ((u64)readl(base + EDPCSR_LO)) |
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((u64)readl(base + EDPCSR_HI) << 32);
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else
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edpcsr = (u32)readl(base + EDPCSR_LO);
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/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
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pc = (void *)(edpcsr & ~1);
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if (pc != prev_pc) {
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output->printf(output,
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"\tPC: <0x%px> %pS\n", pc, pc);
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printed++;
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}
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prev_pc = pc;
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}
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output->printf(output, "\n");
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i++;
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prev_pc = NULL;
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printed = 0;
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}
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rockchip_debug_serror_enable();
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return NOTIFY_OK;
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}
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#ifdef CONFIG_ARM64
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static int rockchip_debug_dump_pmpcsr(struct fiq_debugger_output *output)
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{
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u64 pmpcsr;
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int i = 0, j = 0, el, ns;
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void *pc = NULL;
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void *prev_pc = NULL;
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int printed = 0;
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void __iomem *base;
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u32 pu = 0, online = 0;
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rockchip_debug_serror_disable();
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while (rockchip_cs_pmu[i]) {
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online = cpu_online(i);
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output->printf(output,
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"CPU%d online:%d\n", i, online);
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if (online == 0) {
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i++;
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continue;
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}
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pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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output->printf(output,
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"CPU%d power down\n", i);
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i++;
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continue;
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}
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base = rockchip_cs_pmu[i];
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/* Try to read a bunch of times if CPU is actually running */
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for (j = 0; j < NUM_CPU_SAMPLES &&
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printed < NUM_SAMPLES_TO_PRINT; j++) {
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pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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output->printf(output,
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"CPU%d power down\n", i);
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break;
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}
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pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
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((u64)readl(base + PMPCSR_HI) << 32);
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el = (pmpcsr >> 61) & 0x3;
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if (pmpcsr & 0x8000000000000000)
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ns = 1;
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else
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ns = 0;
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if (el == 2)
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pmpcsr |= 0xff00000000000000;
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else
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pmpcsr &= 0x0fffffffffffffff;
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/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
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pc = (void *)(pmpcsr & ~1);
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if (pc != prev_pc) {
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output->printf(output, "\tEL%d(%s) PC: <0x%px> %pS\n",
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el, ns?"NS":"S", pc, pc);
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printed++;
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}
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prev_pc = pc;
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}
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output->printf(output, "\n");
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i++;
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prev_pc = NULL;
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printed = 0;
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}
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rockchip_debug_serror_enable();
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return NOTIFY_OK;
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}
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#else
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static int rockchip_debug_dump_pmpcsr(struct fiq_debugger_output *output)
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{
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return 0;
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}
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#endif
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int rockchip_debug_dump_pcsr(struct fiq_debugger_output *output)
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{
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if (edpcsr_present)
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rockchip_debug_dump_edpcsr(output);
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else
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rockchip_debug_dump_pmpcsr(output);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rockchip_debug_dump_pcsr);
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#endif
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static int rockchip_panic_notify_edpcsr(struct notifier_block *nb,
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unsigned long event, void *p)
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{
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unsigned long edpcsr;
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int i = 0, j;
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void *pc = NULL;
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void *prev_pc = NULL;
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int printed = 0;
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void __iomem *base;
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u32 pu = 0;
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rockchip_debug_serror_disable();
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/*
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* The panic handler will try to shut down the other CPUs.
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* If any of them are still online at this point, this loop attempts
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* to determine the program counter value. If there are no wedged
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* CPUs, this loop will do nothing.
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*/
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while (rockchip_cpu_debug[i]) {
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base = rockchip_cpu_debug[i];
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pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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pr_err("CPU%d power down\n", i);
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i++;
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continue;
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}
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/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
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writel(EDLAR_UNLOCK, base + EDLAR);
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pr_err("CPU%d online:%d\n", i, cpu_online(i));
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/* Try to read a bunch of times if CPU is actually running */
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for (j = 0; j < NUM_CPU_SAMPLES &&
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printed < NUM_SAMPLES_TO_PRINT; j++) {
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pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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pr_err("CPU%d power down\n", i);
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break;
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}
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if (sizeof(edpcsr) == 8)
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edpcsr = ((u64)readl(base + EDPCSR_LO)) |
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((u64)readl(base + EDPCSR_HI) << 32);
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else
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edpcsr = (u32)readl(base + EDPCSR_LO);
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/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
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pc = (void *)(edpcsr & ~1);
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if (pc != prev_pc) {
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pr_err("\tPC: <0x%px> %pS\n", pc, pc);
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printed++;
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}
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prev_pc = pc;
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}
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pr_err("\n");
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i++;
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prev_pc = NULL;
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printed = 0;
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}
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return NOTIFY_OK;
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}
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#ifdef CONFIG_ARM64
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static int rockchip_panic_notify_pmpcsr(struct notifier_block *nb,
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unsigned long event, void *p)
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{
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u64 pmpcsr;
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int i = 0, j, el, ns;
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void *pc = NULL;
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void *prev_pc = NULL;
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int printed = 0;
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void __iomem *base;
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u32 pu = 0;
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rockchip_debug_serror_disable();
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/*
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* The panic handler will try to shut down the other CPUs.
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* If any of them are still online at this point, this loop attempts
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* to determine the program counter value. If there are no wedged
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* CPUs, this loop will do nothing.
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*/
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while (rockchip_cs_pmu[i]) {
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base = rockchip_cs_pmu[i];
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pr_err("CPU%d online:%d\n", i, cpu_online(i));
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pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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pr_err("CPU%d power down\n", i);
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i++;
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continue;
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}
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/* Try to read a bunch of times if CPU is actually running */
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for (j = 0; j < NUM_CPU_SAMPLES &&
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printed < NUM_SAMPLES_TO_PRINT; j++) {
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pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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pr_err("CPU%d power down\n", i);
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break;
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}
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pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
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((u64)readl(base + PMPCSR_HI) << 32);
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el = (pmpcsr >> 61) & 0x3;
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if (pmpcsr & 0x8000000000000000)
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ns = 1;
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else
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ns = 0;
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if (el == 2)
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pmpcsr |= 0xff00000000000000;
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else
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pmpcsr &= 0x0fffffffffffffff;
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/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
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pc = (void *)(pmpcsr & ~1);
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if (pc != prev_pc) {
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pr_err("\tEL%d(%s) PC: <0x%px> %pS\n",
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el, ns?"NS":"S", pc, pc);
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printed++;
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}
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prev_pc = pc;
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}
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pr_err("\n");
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i++;
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prev_pc = NULL;
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printed = 0;
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}
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return NOTIFY_OK;
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}
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#else
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static int rockchip_panic_notify_pmpcsr(struct notifier_block *nb,
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unsigned long event, void *p)
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{
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return NOTIFY_OK;
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}
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#endif
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static int rockchip_show_interrupts(char *p, int irq)
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{
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static int prec;
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char *buf = p;
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unsigned long any_count = 0;
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int i = irq, j;
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struct irqaction *action;
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struct irq_desc *desc;
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if (i > nr_irqs)
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return -1;
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/* print header and calculate the width of the first column */
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if (i == 0) {
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for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
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j *= 10;
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buf += sprintf(buf, "%*s", prec + 8, "");
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for_each_possible_cpu(j)
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buf += sprintf(buf, "CPU%-8d", j);
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buf += sprintf(buf, "\n");
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}
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desc = irq_to_desc(i);
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if (!desc || (desc->status_use_accessors & IRQ_HIDDEN))
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goto outsparse;
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if (desc->kstat_irqs)
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for_each_possible_cpu(j)
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any_count |= *per_cpu_ptr(desc->kstat_irqs, j);
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if ((!desc->action) && !any_count)
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goto outsparse;
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buf += sprintf(buf, "%*d: ", prec, i);
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for_each_possible_cpu(j)
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buf += sprintf(buf, "%10u ", desc->kstat_irqs ?
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*per_cpu_ptr(desc->kstat_irqs, j) : 0);
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if (desc->irq_data.chip) {
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if (desc->irq_data.chip->name)
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buf += sprintf(buf, " %8s", desc->irq_data.chip->name);
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else
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buf += sprintf(buf, " %8s", "-");
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} else {
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buf += sprintf(buf, " %8s", "None");
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}
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if (desc->irq_data.domain)
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buf += sprintf(buf, " %*lu", prec, desc->irq_data.hwirq);
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else
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buf += sprintf(buf, " %*s", prec, "");
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#ifdef CONFIG_GENERIC_IRQ_SHOW_LEVEL
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buf += sprintf(buf, " %-8s", irqd_is_level_type(&desc->irq_data) ? "Level" : "Edge");
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#endif
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if (desc->name)
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buf += sprintf(buf, "-%-8s", desc->name);
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action = desc->action;
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if (action) {
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buf += sprintf(buf, " %s", action->name);
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while ((action = action->next) != NULL)
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buf += sprintf(buf, ", %s", action->name);
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}
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sprintf(buf, "\n");
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return 0;
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outsparse:
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return -1;
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}
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static void rockchip_panic_notify_dump_irqs(void)
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{
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int i = 0;
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for (i = 0; i < nr_irqs; i++) {
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if (!rockchip_show_interrupts(log_buf, i) || i == 0)
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printk("%s", log_buf);
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}
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}
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static int rockchip_panic_notify(struct notifier_block *nb, unsigned long event,
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void *p)
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{
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if (edpcsr_present)
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rockchip_panic_notify_edpcsr(nb, event, p);
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else
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rockchip_panic_notify_pmpcsr(nb, event, p);
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rockchip_panic_notify_dump_irqs();
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mdelay(1000);
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rockchip_panic_notify_dump_irqs();
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return NOTIFY_OK;
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}
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static int rockchip_hardlock_notify(struct notifier_block *nb,
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unsigned long event, void *p)
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{
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u64 pmpcsr;
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int el;
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u32 pu = 0;
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void *pc = NULL;
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void __iomem *base;
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unsigned long edpcsr;
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unsigned long cpu = event;
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rockchip_debug_serror_disable();
|
|
|
|
pu = (u32)readl(rockchip_cpu_debug[cpu] + EDPRSR) & EDPRSR_PU;
|
|
if (pu != EDPRSR_PU) {
|
|
pr_err("CPU%ld power down\n", cpu);
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
if (edpcsr_present) {
|
|
base = rockchip_cpu_debug[cpu];
|
|
/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
|
|
writel(EDLAR_UNLOCK, base + EDLAR);
|
|
if (sizeof(edpcsr) == 8)
|
|
edpcsr = ((u64)readl(base + EDPCSR_LO)) |
|
|
((u64)readl(base + EDPCSR_HI) << 32);
|
|
else
|
|
edpcsr = (u32)readl(base + EDPCSR_LO);
|
|
|
|
/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
|
|
pc = (void *)(edpcsr & ~1);
|
|
} else {
|
|
base = rockchip_cs_pmu[cpu];
|
|
pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
|
|
((u64)readl(base + PMPCSR_HI) << 32);
|
|
el = (pmpcsr >> 61) & 0x3;
|
|
if (el == 2)
|
|
pmpcsr |= 0xff00000000000000;
|
|
else
|
|
pmpcsr &= 0x0fffffffffffffff;
|
|
/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
|
|
pc = (void *)(uintptr_t)(pmpcsr & ~1);
|
|
}
|
|
|
|
rockchip_debug_serror_enable();
|
|
|
|
#if IS_ENABLED(CONFIG_ROCKCHIP_MINIDUMP)
|
|
rk_minidump_hardlock_notify(nb, event, pc);
|
|
#endif
|
|
|
|
#if !IS_ENABLED(CONFIG_BOOTPARAM_HARDLOCKUP_PANIC)
|
|
rockchip_panic_notify(nb, event, p);
|
|
#endif
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block rockchip_panic_nb = {
|
|
.notifier_call = rockchip_panic_notify,
|
|
};
|
|
|
|
static struct notifier_block rockchip_rcu_stall_nb = {
|
|
.notifier_call = rockchip_panic_notify,
|
|
};
|
|
|
|
static struct notifier_block rockchip_hardlock_nb = {
|
|
.notifier_call = rockchip_hardlock_notify,
|
|
};
|
|
|
|
static const struct of_device_id rockchip_debug_dt_match[] __initconst = {
|
|
/* external debug */
|
|
{
|
|
.compatible = "rockchip,debug",
|
|
},
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static const struct of_device_id rockchip_cspmu_dt_match[] __initconst = {
|
|
/* coresight pmu */
|
|
{
|
|
.compatible = "rockchip,cspmu",
|
|
},
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static int __init rockchip_debug_init(void)
|
|
{
|
|
int i;
|
|
u32 pcs;
|
|
struct device_node *debug_np = NULL, *cspmu_np = NULL;
|
|
|
|
debug_np = of_find_matching_node_and_match(NULL,
|
|
rockchip_debug_dt_match, NULL);
|
|
|
|
if (debug_np) {
|
|
i = -1;
|
|
do {
|
|
i++;
|
|
rockchip_cpu_debug[i] = of_iomap(debug_np, i);
|
|
} while (rockchip_cpu_debug[i]);
|
|
of_node_put(debug_np);
|
|
}
|
|
|
|
cspmu_np = of_find_matching_node_and_match(NULL,
|
|
rockchip_cspmu_dt_match, NULL);
|
|
|
|
if (cspmu_np) {
|
|
i = -1;
|
|
do {
|
|
i++;
|
|
rockchip_cs_pmu[i] = of_iomap(cspmu_np, i);
|
|
} while (rockchip_cs_pmu[i]);
|
|
of_node_put(cspmu_np);
|
|
}
|
|
|
|
if (!debug_np)
|
|
return -ENODEV;
|
|
|
|
pcs = readl(rockchip_cpu_debug[0] + EDDEVID) & 0xf;
|
|
/* 0x3 EDPCSR, EDCIDSR, and EDVIDSR are implemented */
|
|
if (pcs == 0x3)
|
|
edpcsr_present = true;
|
|
|
|
if (!edpcsr_present && !cspmu_np)
|
|
return -ENODEV;
|
|
|
|
atomic_notifier_chain_register(&panic_notifier_list,
|
|
&rockchip_panic_nb);
|
|
if (IS_ENABLED(CONFIG_NO_GKI)) {
|
|
if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
|
|
atomic_notifier_chain_register(&hardlock_notifier_list,
|
|
&rockchip_hardlock_nb);
|
|
|
|
atomic_notifier_chain_register(&rcu_stall_notifier_list,
|
|
&rockchip_rcu_stall_nb);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(rockchip_debug_init);
|
|
|
|
static void __exit rockchip_debug_exit(void)
|
|
{
|
|
int i = 0;
|
|
|
|
atomic_notifier_chain_unregister(&panic_notifier_list,
|
|
&rockchip_panic_nb);
|
|
if (IS_ENABLED(CONFIG_NO_GKI)) {
|
|
if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
|
|
atomic_notifier_chain_unregister(&hardlock_notifier_list,
|
|
&rockchip_hardlock_nb);
|
|
|
|
atomic_notifier_chain_unregister(&rcu_stall_notifier_list,
|
|
&rockchip_rcu_stall_nb);
|
|
}
|
|
|
|
while (rockchip_cpu_debug[i])
|
|
iounmap(rockchip_cpu_debug[i++]);
|
|
|
|
i = 0;
|
|
while (rockchip_cs_pmu[i])
|
|
iounmap(rockchip_cs_pmu[i++]);
|
|
}
|
|
module_exit(rockchip_debug_exit);
|
|
|
|
MODULE_AUTHOR("Huibin Hong <huibin.hong@rock-chips.com>");
|
|
MODULE_DESCRIPTION("Rockchip Debugger");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:rockchip-debugger");
|