168 lines
4.6 KiB
YAML
168 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek Video Decode Accelerator
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maintainers:
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- Yunfei Dong <yunfei.dong@mediatek.com>
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description: |+
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Mediatek Video Decode is the video decode hardware present in Mediatek
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SoCs which supports high resolution decoding functionalities.
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properties:
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compatible:
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enum:
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- mediatek,mt8173-vcodec-dec
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- mediatek,mt8183-vcodec-dec
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reg:
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maxItems: 12
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 8
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clock-names:
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items:
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- const: vcodecpll
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- const: univpll_d2
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- const: clk_cci400_sel
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- const: vdec_sel
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- const: vdecpll
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- const: vencpll
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- const: venc_lt_sel
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- const: vdec_bus_clk_src
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assigned-clocks: true
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assigned-clock-parents: true
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assigned-clock-rates: true
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power-domains:
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maxItems: 1
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iommus:
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minItems: 1
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maxItems: 32
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description: |
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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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mediatek,vpu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Describes point to vpu.
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mediatek,scp:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Describes point to scp.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- iommus
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- assigned-clocks
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- assigned-clock-parents
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8183-vcodec-dec
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then:
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required:
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- mediatek,scp
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8173-vcodec-dec
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then:
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required:
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- mediatek,vpu
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/memory/mt8173-larb-port.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt8173-power.h>
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vcodec_dec: vcodec@16000000 {
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compatible = "mediatek,mt8173-vcodec-dec";
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reg = <0x16000000 0x100>, /*VDEC_SYS*/
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<0x16020000 0x1000>, /*VDEC_MISC*/
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<0x16021000 0x800>, /*VDEC_LD*/
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<0x16021800 0x800>, /*VDEC_TOP*/
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<0x16022000 0x1000>, /*VDEC_CM*/
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<0x16023000 0x1000>, /*VDEC_AD*/
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<0x16024000 0x1000>, /*VDEC_AV*/
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<0x16025000 0x1000>, /*VDEC_PP*/
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<0x16026800 0x800>, /*VP8_VD*/
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<0x16027000 0x800>, /*VP6_VD*/
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<0x16027800 0x800>, /*VP8_VL*/
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<0x16028400 0x400>; /*VP9_VD*/
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
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<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
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<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
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mediatek,vpu = <&vpu>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_CCI400_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>,
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<&topckgen CLK_TOP_VCODECPLL>,
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<&apmixedsys CLK_APMIXED_VENCPLL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>,
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<&topckgen CLK_TOP_VCODECPLL_370P5>;
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clock-names = "vcodecpll",
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"univpll_d2",
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"clk_cci400_sel",
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"vdec_sel",
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"vdecpll",
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"vencpll",
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"venc_lt_sel",
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"vdec_bus_clk_src";
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assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
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<&topckgen CLK_TOP_CCI400_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>,
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<&apmixedsys CLK_APMIXED_VCODECPLL>,
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<&apmixedsys CLK_APMIXED_VENCPLL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_VCODECPLL>;
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assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
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};
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