86 lines
2.2 KiB
YAML
86 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Write DMA with Rotation
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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- Moudy Ho <moudy.ho@mediatek.com>
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description: |
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One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8183-mdp3-wrot
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reg:
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maxItems: 1
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mediatek,gce-client-reg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property. Each GCE subsys id is mapping to
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a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
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mediatek,gce-events:
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description:
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The event id which is mapping to the specific hardware event signal
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to gce. The event id is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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power-domains:
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maxItems: 1
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clocks:
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minItems: 1
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iommus:
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maxItems: 1
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'#dma-cells':
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const: 1
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required:
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- compatible
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- reg
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- mediatek,gce-client-reg
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- mediatek,gce-events
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- power-domains
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- clocks
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- iommus
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- '#dma-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/memory/mt8183-larb-port.h>
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dma-controller@14005000 {
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compatible = "mediatek,mt8183-mdp3-wrot";
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reg = <0x14005000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
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<CMDQ_EVENT_MDP_WROT0_EOF>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_MDP_WROT0>;
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iommus = <&iommu>;
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#dma-cells = <1>;
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};
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