83 lines
2.6 KiB
Plaintext
83 lines
2.6 KiB
Plaintext
STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
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MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
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time. Active port input stream will be de-serialized and its content outputted
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through PARALLEL output port.
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CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
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input port is a single lane 800Mbps. Both ports support clock and data lane
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polarity swap. First port also supports data lane swap.
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PARALLEL output port has a maximum width of 12 bits.
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Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
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YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
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Required Properties:
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- compatible: shall be "st,st-mipid02"
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- clocks: reference to the xclk input clock.
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- clock-names: shall be "xclk".
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- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
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- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
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Optional Properties:
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- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
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This is an active low signal to the mipid02.
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Required subnodes:
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- ports: A ports node with one port child node per device input and output
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port, in accordance with the video interface bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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port nodes are numbered as follows:
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Port Description
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-----------------------------
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0 CSI-2 first input port
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1 CSI-2 second input port
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2 PARALLEL output
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Endpoint node required property for CSI-2 connection is:
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- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
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<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
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Endpoint node optional property for CSI-2 connection is:
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- lane-polarities: any lane can be inverted or not.
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Endpoint node required property for PARALLEL connection is:
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- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.
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Endpoint node optional properties for PARALLEL connection are:
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- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
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LOW being the default.
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- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
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LOW being the default.
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Example:
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mipid02: csi2rx@14 {
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compatible = "st,st-mipid02";
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reg = <0x14>;
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status = "okay";
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clocks = <&clk_ext_camera_12>;
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clock-names = "xclk";
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VDDE-supply = <&vdd>;
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VDDIN-supply = <&vdd>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ep0: endpoint {
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data-lanes = <1 2>;
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remote-endpoint = <&mipi_csi2_in>;
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};
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};
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port@2 {
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reg = <2>;
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ep2: endpoint {
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bus-width = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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remote-endpoint = <¶llel_out>;
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};
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};
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};
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};
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