131 lines
4.9 KiB
Plaintext
131 lines
4.9 KiB
Plaintext
* rk3399 dram default timing is at arch/arm64/boot/dts/rk3399_dram_default_timing.dtsi
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Required properties:
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- compatible : Should be "rockchip,ddr-timing"
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- ddr3_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h.
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It select DDR3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected
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according to "Speed Bin" in DDR3 datasheet, DO NOT use smaller "Speed Bin" than
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DDR3 exactly is.
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- pd_idle : Defines the power-down mode auto entry controller clocks.
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This parameter defines the number of idle controller clocks that can elapse
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before the controller will automatically issue an entry into the appropriate
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power-down low power state.
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- sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating
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auto entry periodic cycles.
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This parameter defines the number of long count sequences that can elapse
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before the controller will automatically issue an entry into the Self-Refresh
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or Self-Refresh with Memory Clock Gating low power state.
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- sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating
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auto entry periodic cycles.
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This parameter defines the number of long count sequences that can elapse before
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the controller will automatically issue an entry into the Self-Refresh with
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Memory and Controller Clock Gating low power state.
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- srpd_lite_idle : Define the Lite Self-Refresh Power-Down auto entry periodic
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cycles.
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This parameter defines the number of long count sequences that can elapse
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before the controller will automatically issue an entry into the
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Lite Self-Refresh Power-Down low power state.
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- standby_idle : Define the standby mode auto entry periodic cycles.
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- auto_lp_dis_freq : It's defined the auto low down mode frequency in MHz (Mega Hz),
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when ddr freq greater than or equal this setting value, auto power-down will disable.
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- ddr3_dll_dis_freq : It's defined the DDR3 dll bypass frequency in MHz (Mega Hz),
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when ddr freq less than or equal this setting value, DDR3 dll will bypssed.
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note: if dll was bypassed, the odt also stop working.
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- phy_dll_dis_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz),
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when ddr freq less than or equal this setting value, phy dll will bypssed.
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note: phy dll and phy odt are independent.
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- ddr3_odt_dis_freq : Defined the DDR3 odt disable frequency in
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MHz (Mega Hz), when ddr frequency less then or equal ethis setting value, the DDR3
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ODT are disabled.
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- ddr3_drv : Define the driver strength in ohm when connect DDR3.
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- ddr3_odt : Define the ODT in ohm when connect DDR3.
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- phy_ddr3_ca_drv : Define the PHY CA driver strength in ohm when connect DDR3.
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- phy_ddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect DDR3.
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- phy_ddr3_odt : Define the phy odt in ohm when connect DDR3.
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- lpddr3_odt_dis_freq : Defined the LPDDR3 odt disable frequency in
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MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR3
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ODT are disabled.
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- lpddr3_drv : Define the driver strength in ohm when connect LPDDR3.
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- lpddr3_odt : Define the ODT in ohm when connect LPDDR3.
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- phy_lpddr3_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR3.
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- phy_lpddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR3.
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- phy_lpddr3_odt : Define the phy odt in ohm when connect LPDDR3.
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- lpddr4_odt_dis_freq : Defined the LPDDR4 odt disable frequency in
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MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR4
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ODT are disabled.
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- lpddr4_drv : Define the driver strength in ohm when connect LPDDR4.
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- lpddr4_dq_odt : Define the DQ ODT in ohm when connect LPDDR4.
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- lpddr4_ca_odt : Define the CA ODT in ohm when connect LPDDR4.
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- phy_lpddr4_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR4.
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- phy_lpddr4_ck_cs_drv : Define the PHY CLK and CS driver strength in ohm when connect LPDDR4.
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- phy_lpddr4_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR4.
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- phy_lpddr4_odt : Define the phy odt in ohm when connect LPDDR4.
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Example:
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <21>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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auto_lp_dis_freq = <666>;
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ddr3_dll_dis_freq = <300>;
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phy_dll_dis_freq = <260>;
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ddr3_odt_dis_freq = <666>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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phy_ddr3_odt = <PHY_DRV_ODT_240>;
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lpddr3_odt_dis_freq = <666>;
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lpddr3_drv = <LP3_DS_34ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>;
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phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>;
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phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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lpddr4_odt_dis_freq = <933>;
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lpddr4_drv = <LP4_PDDS_60ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
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phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
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phy_lpddr4_odt = <PHY_DRV_ODT_60>;
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};
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};
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