621 lines
16 KiB
C
621 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 SiFive, Inc.
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* Copyright (C) 2020 Zong Li
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include "sifive-prci.h"
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#include "fu540-prci.h"
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#include "fu740-prci.h"
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/*
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* Private functions
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*/
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/**
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* __prci_readl() - read from a PRCI register
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* @pd: PRCI context
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* @offs: register offset to read from (in bytes, from PRCI base address)
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*
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* Read the register located at offset @offs from the base virtual
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* address of the PRCI register target described by @pd, and return
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* the value to the caller.
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*
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* Context: Any context.
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*
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* Return: the contents of the register described by @pd and @offs.
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*/
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static u32 __prci_readl(struct __prci_data *pd, u32 offs)
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{
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return readl_relaxed(pd->va + offs);
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}
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static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
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{
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writel_relaxed(v, pd->va + offs);
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}
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/* WRPLL-related private functions */
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/**
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* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
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* @c: ptr to a struct wrpll_cfg record to write config into
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* @r: value read from the PRCI PLL configuration register
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*
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* Given a value @r read from an FU740 PRCI PLL configuration register,
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* split it into fields and populate it into the WRPLL configuration record
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* pointed to by @c.
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*
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* The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
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* have the same register layout.
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*
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* Context: Any context.
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*/
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static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
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{
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u32 v;
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v = r & PRCI_COREPLLCFG0_DIVR_MASK;
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v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
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c->divr = v;
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v = r & PRCI_COREPLLCFG0_DIVF_MASK;
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v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
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c->divf = v;
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v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
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v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
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c->divq = v;
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v = r & PRCI_COREPLLCFG0_RANGE_MASK;
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v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
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c->range = v;
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c->flags &=
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(WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK);
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/* external feedback mode not supported */
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c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
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}
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/**
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* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
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* @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
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*
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* Using a set of WRPLL configuration values pointed to by @c,
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* assemble a PRCI PLL configuration register value, and return it to
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* the caller.
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*
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* Context: Any context. Caller must ensure that the contents of the
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* record pointed to by @c do not change during the execution
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* of this function.
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*
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* Returns: a value suitable for writing into a PRCI PLL configuration
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* register
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*/
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static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
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{
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u32 r = 0;
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r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
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r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
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r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
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r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
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/* external feedback mode not supported */
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r |= PRCI_COREPLLCFG0_FSE_MASK;
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return r;
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}
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/**
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* __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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*
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* Read the current configuration of the PLL identified by @pwd from
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* the PRCI identified by @pd, and store it into the local configuration
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* cache in @pwd.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd)
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{
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__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
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}
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/**
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* __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @c: WRPLL configuration record to write
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*
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* Write the WRPLL configuration described by @c into the WRPLL
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* configuration register identified by @pwd in the PRCI instance
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* described by @c. Make a cached copy of the WRPLL's current
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* configuration so it can be used by other code.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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struct wrpll_cfg *c)
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{
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__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
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memcpy(&pwd->c, c, sizeof(*c));
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}
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/**
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* __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
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* into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @enable: Clock enable or disable value
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*/
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static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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u32 enable)
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{
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__prci_writel(enable, pwd->cfg1_offs, pd);
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}
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/*
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* Linux clock framework integration
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*
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* See the Linux clock framework documentation for more information on
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* these functions.
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*/
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unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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return wrpll_calc_output_rate(&pwd->c, parent_rate);
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}
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long sifive_prci_wrpll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct wrpll_cfg c;
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memcpy(&c, &pwd->c, sizeof(c));
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wrpll_configure_for_rate(&c, rate, *parent_rate);
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return wrpll_calc_output_rate(&c, *parent_rate);
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}
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int sifive_prci_wrpll_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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int r;
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r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
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if (r)
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return r;
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if (pwd->enable_bypass)
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pwd->enable_bypass(pd);
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__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
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udelay(wrpll_calc_max_lock_us(&pwd->c));
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return 0;
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}
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int sifive_clk_is_enabled(struct clk_hw *hw)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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u32 r;
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r = __prci_readl(pd, pwd->cfg1_offs);
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if (r & PRCI_COREPLLCFG1_CKE_MASK)
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return 1;
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else
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return 0;
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}
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int sifive_prci_clock_enable(struct clk_hw *hw)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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if (sifive_clk_is_enabled(hw))
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return 0;
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__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
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if (pwd->disable_bypass)
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pwd->disable_bypass(pd);
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return 0;
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}
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void sifive_prci_clock_disable(struct clk_hw *hw)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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u32 r;
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if (pwd->enable_bypass)
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pwd->enable_bypass(pd);
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r = __prci_readl(pd, pwd->cfg1_offs);
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r &= ~PRCI_COREPLLCFG1_CKE_MASK;
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__prci_wrpll_write_cfg1(pd, pwd, r);
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}
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/* TLCLKSEL clock integration */
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unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_data *pd = pc->pd;
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u32 v;
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u8 div;
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v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
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v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
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div = v ? 1 : 2;
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return div_u64(parent_rate, div);
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}
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/* HFPCLK clock integration */
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unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_data *pd = pc->pd;
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u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);
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return div_u64(parent_rate, div + 2);
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}
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/*
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* Core clock mux control
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*/
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/**
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* sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the HFCLK input source; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
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* COREPLL
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the COREPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
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* FINAL_COREPLL
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the final COREPLL output clock; return once
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* complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
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* output DVFS_COREPLL
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* @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
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*
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* Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_COREPLLSEL_OFFSET register.
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*/
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void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
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r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;
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__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
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* output COREPLL
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* @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
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*
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* Switch the COREPLL mux to the COREPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_COREPLLSEL_OFFSET register.
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*/
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void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
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r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;
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__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
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* output HFCLK
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* @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
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*
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* Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_HFPCLKPLLSEL_OFFSET register.
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*/
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void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
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r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
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__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
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* output HFPCLKPLL
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* @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
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*
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* Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_HFPCLKPLLSEL_OFFSET register.
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*/
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void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
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r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
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__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
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}
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/* PCIE AUX clock APIs for enable, disable. */
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int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_data *pd = pc->pd;
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u32 r;
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r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);
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if (r & PRCI_PCIE_AUX_EN_MASK)
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return 1;
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else
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return 0;
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}
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int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_data *pd = pc->pd;
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u32 r __maybe_unused;
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if (sifive_prci_pcie_aux_clock_is_enabled(hw))
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return 0;
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__prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);
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r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
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return 0;
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}
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void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw)
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{
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struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
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struct __prci_data *pd = pc->pd;
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u32 r __maybe_unused;
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__prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);
|
|
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
|
|
|
|
}
|
|
|
|
/**
|
|
* __prci_register_clocks() - register clock controls in the PRCI
|
|
* @dev: Linux struct device
|
|
* @pd: The pointer for PRCI per-device instance data
|
|
* @desc: The pointer for the information of clocks of each SoCs
|
|
*
|
|
* Register the list of clock controls described in __prci_init_clocks[] with
|
|
* the Linux clock framework.
|
|
*
|
|
* Return: 0 upon success or a negative error code upon failure.
|
|
*/
|
|
static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,
|
|
const struct prci_clk_desc *desc)
|
|
{
|
|
struct clk_init_data init = { };
|
|
struct __prci_clock *pic;
|
|
int parent_count, i, r;
|
|
|
|
parent_count = of_clk_get_parent_count(dev->of_node);
|
|
if (parent_count != EXPECTED_CLK_PARENT_COUNT) {
|
|
dev_err(dev, "expected only two parent clocks, found %d\n",
|
|
parent_count);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Register PLLs */
|
|
for (i = 0; i < desc->num_clks; ++i) {
|
|
pic = &(desc->clks[i]);
|
|
|
|
init.name = pic->name;
|
|
init.parent_names = &pic->parent_name;
|
|
init.num_parents = 1;
|
|
init.ops = pic->ops;
|
|
pic->hw.init = &init;
|
|
|
|
pic->pd = pd;
|
|
|
|
if (pic->pwd)
|
|
__prci_wrpll_read_cfg0(pd, pic->pwd);
|
|
|
|
r = devm_clk_hw_register(dev, &pic->hw);
|
|
if (r) {
|
|
dev_warn(dev, "Failed to register clock %s: %d\n",
|
|
init.name, r);
|
|
return r;
|
|
}
|
|
|
|
pd->hw_clks.hws[i] = &pic->hw;
|
|
}
|
|
|
|
pd->hw_clks.num = i;
|
|
|
|
r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
|
&pd->hw_clks);
|
|
if (r) {
|
|
dev_err(dev, "could not add hw_provider: %d\n", r);
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* sifive_prci_probe() - initialize prci data and check parent count
|
|
* @pdev: platform device pointer for the prci
|
|
*
|
|
* Return: 0 upon success or a negative error code upon failure.
|
|
*/
|
|
static int sifive_prci_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res;
|
|
struct __prci_data *pd;
|
|
const struct prci_clk_desc *desc;
|
|
int r;
|
|
|
|
desc = of_device_get_match_data(&pdev->dev);
|
|
|
|
pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);
|
|
if (!pd)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
pd->va = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(pd->va))
|
|
return PTR_ERR(pd->va);
|
|
|
|
pd->reset.rcdev.owner = THIS_MODULE;
|
|
pd->reset.rcdev.nr_resets = PRCI_RST_NR;
|
|
pd->reset.rcdev.ops = &reset_simple_ops;
|
|
pd->reset.rcdev.of_node = pdev->dev.of_node;
|
|
pd->reset.active_low = true;
|
|
pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
|
|
spin_lock_init(&pd->reset.lock);
|
|
|
|
r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
|
|
if (r) {
|
|
dev_err(dev, "could not register reset controller: %d\n", r);
|
|
return r;
|
|
}
|
|
r = __prci_register_clocks(dev, pd, desc);
|
|
if (r) {
|
|
dev_err(dev, "could not register clocks: %d\n", r);
|
|
return r;
|
|
}
|
|
|
|
dev_dbg(dev, "SiFive PRCI probed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sifive_prci_of_match[] = {
|
|
{.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540},
|
|
{.compatible = "sifive,fu740-c000-prci", .data = &prci_clk_fu740},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver sifive_prci_driver = {
|
|
.driver = {
|
|
.name = "sifive-clk-prci",
|
|
.of_match_table = sifive_prci_of_match,
|
|
},
|
|
.probe = sifive_prci_probe,
|
|
};
|
|
|
|
static int __init sifive_prci_init(void)
|
|
{
|
|
return platform_driver_register(&sifive_prci_driver);
|
|
}
|
|
core_initcall(sifive_prci_init);
|