131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv04.h"
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#include "channv04.h"
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#include "regsnv04.h"
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#include <core/ramht.h>
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#include <subdev/fb.h>
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#include <subdev/instmem.h>
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static const struct nv04_fifo_ramfc
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nv40_fifo_ramfc[] = {
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{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
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{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
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{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
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{ 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
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{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
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{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE },
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{ 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
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{ 2, 28, 0x18, 28, 0x002058 },
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{ 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE },
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{ 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 },
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{ 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
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{ 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
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{ 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
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{ 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
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{ 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
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{ 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE },
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{ 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE },
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{ 32, 0, 0x40, 0, 0x0032e4 },
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{ 32, 0, 0x44, 0, 0x0032e8 },
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{ 32, 0, 0x4c, 0, 0x002088 },
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{ 32, 0, 0x50, 0, 0x003300 },
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{ 32, 0, 0x54, 0, 0x00330c },
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{}
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};
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static void
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nv40_fifo_init(struct nvkm_fifo *base)
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{
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struct nv04_fifo *fifo = nv04_fifo(base);
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_fb *fb = device->fb;
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struct nvkm_instmem *imem = device->imem;
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struct nvkm_ramht *ramht = imem->ramht;
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struct nvkm_memory *ramro = imem->ramro;
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struct nvkm_memory *ramfc = imem->ramfc;
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nvkm_wr32(device, 0x002040, 0x000000ff);
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nvkm_wr32(device, 0x002044, 0x2101ffff);
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nvkm_wr32(device, 0x002058, 0x00000001);
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nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
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((ramht->bits - 9) << 16) |
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(ramht->gpuobj->addr >> 8));
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nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
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switch (device->chipset) {
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case 0x47:
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case 0x49:
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case 0x4b:
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nvkm_wr32(device, 0x002230, 0x00000001);
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fallthrough;
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x45:
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case 0x48:
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nvkm_wr32(device, 0x002220, 0x00030002);
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break;
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default:
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nvkm_wr32(device, 0x002230, 0x00000000);
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nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +
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nvkm_memory_addr(ramfc)) >> 16) |
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0x00030000);
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break;
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}
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);
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nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
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nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
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nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
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nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
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}
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static const struct nvkm_fifo_func
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nv40_fifo = {
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.init = nv40_fifo_init,
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.intr = nv04_fifo_intr,
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.engine_id = nv04_fifo_engine_id,
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.id_engine = nv04_fifo_id_engine,
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.pause = nv04_fifo_pause,
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.start = nv04_fifo_start,
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.chan = {
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&nv40_fifo_dma_oclass,
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NULL
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},
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};
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int
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nv40_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_fifo **pfifo)
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{
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return nv04_fifo_new_(&nv40_fifo, device, type, inst, 32, nv40_fifo_ramfc, pfifo);
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}
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