312 lines
8.3 KiB
C
312 lines
8.3 KiB
C
/*
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* Copyright 2021 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#define ga102_fifo(p) container_of((p), struct ga102_fifo, base.engine)
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#define ga102_chan(p) container_of((p), struct ga102_chan, object)
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#include <engine/fifo.h>
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#include "user.h"
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#include <core/memory.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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#include <subdev/top.h>
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#include <nvif/cl0080.h>
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#include <nvif/clc36f.h>
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#include <nvif/class.h>
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struct ga102_fifo {
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struct nvkm_fifo base;
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};
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struct ga102_chan {
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struct nvkm_object object;
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struct {
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u32 runl;
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u32 chan;
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} ctrl;
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struct nvkm_memory *mthd;
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struct nvkm_memory *inst;
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struct nvkm_memory *user;
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struct nvkm_memory *runl;
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struct nvkm_vmm *vmm;
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};
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static int
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ga102_chan_sclass(struct nvkm_object *object, int index, struct nvkm_oclass *oclass)
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{
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if (index == 0) {
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oclass->ctor = nvkm_object_new;
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oclass->base = (struct nvkm_sclass) { -1, -1, AMPERE_DMA_COPY_B };
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return 0;
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}
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return -EINVAL;
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}
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static int
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ga102_chan_map(struct nvkm_object *object, void *argv, u32 argc,
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enum nvkm_object_map *type, u64 *addr, u64 *size)
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{
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struct ga102_chan *chan = ga102_chan(object);
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struct nvkm_device *device = chan->object.engine->subdev.device;
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u64 bar2 = nvkm_memory_bar2(chan->user);
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if (bar2 == ~0ULL)
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return -EFAULT;
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*type = NVKM_OBJECT_MAP_IO;
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*addr = device->func->resource_addr(device, 3) + bar2;
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*size = 0x1000;
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return 0;
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}
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static int
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ga102_chan_fini(struct nvkm_object *object, bool suspend)
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{
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struct ga102_chan *chan = ga102_chan(object);
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struct nvkm_device *device = chan->object.engine->subdev.device;
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nvkm_wr32(device, chan->ctrl.chan, 0x00000003);
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nvkm_wr32(device, chan->ctrl.runl + 0x098, 0x01000000);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, chan->ctrl.runl + 0x098) & 0x00100000))
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break;
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);
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nvkm_wr32(device, chan->ctrl.runl + 0x088, 0);
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nvkm_wr32(device, chan->ctrl.chan, 0xffffffff);
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return 0;
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}
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static int
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ga102_chan_init(struct nvkm_object *object)
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{
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struct ga102_chan *chan = ga102_chan(object);
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struct nvkm_device *device = chan->object.engine->subdev.device;
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nvkm_mask(device, chan->ctrl.runl + 0x300, 0x80000000, 0x80000000);
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nvkm_wr32(device, chan->ctrl.runl + 0x080, lower_32_bits(nvkm_memory_addr(chan->runl)));
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nvkm_wr32(device, chan->ctrl.runl + 0x084, upper_32_bits(nvkm_memory_addr(chan->runl)));
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nvkm_wr32(device, chan->ctrl.runl + 0x088, 2);
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nvkm_wr32(device, chan->ctrl.chan, 0x00000002);
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nvkm_wr32(device, chan->ctrl.runl + 0x0090, 0);
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return 0;
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}
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static void *
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ga102_chan_dtor(struct nvkm_object *object)
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{
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struct ga102_chan *chan = ga102_chan(object);
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if (chan->vmm) {
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nvkm_vmm_part(chan->vmm, chan->inst);
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nvkm_vmm_unref(&chan->vmm);
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}
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nvkm_memory_unref(&chan->runl);
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nvkm_memory_unref(&chan->user);
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nvkm_memory_unref(&chan->inst);
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nvkm_memory_unref(&chan->mthd);
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return chan;
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}
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static const struct nvkm_object_func
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ga102_chan = {
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.dtor = ga102_chan_dtor,
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.init = ga102_chan_init,
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.fini = ga102_chan_fini,
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.map = ga102_chan_map,
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.sclass = ga102_chan_sclass,
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};
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static int
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ga102_chan_new(struct nvkm_device *device,
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const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject)
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{
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struct volta_channel_gpfifo_a_v0 *args = argv;
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struct nvkm_top_device *tdev;
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struct nvkm_vmm *vmm;
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struct ga102_chan *chan;
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int ret;
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if (argc != sizeof(*args))
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return -ENOSYS;
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vmm = nvkm_uvmm_search(oclass->client, args->vmm);
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if (IS_ERR(vmm))
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return PTR_ERR(vmm);
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_object_ctor(&ga102_chan, oclass, &chan->object);
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*pobject = &chan->object;
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list_for_each_entry(tdev, &device->top->device, head) {
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if (tdev->type == NVKM_ENGINE_CE) {
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chan->ctrl.runl = tdev->runlist;
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break;
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}
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}
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if (!chan->ctrl.runl)
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return -ENODEV;
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chan->ctrl.chan = nvkm_rd32(device, chan->ctrl.runl + 0x004) & 0xfffffff0;
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args->chid = 0;
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args->inst = 0;
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args->token = nvkm_rd32(device, chan->ctrl.runl + 0x008) & 0xffff0000;
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->mthd);
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if (ret)
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return ret;
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->inst);
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if (ret)
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return ret;
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x010, 0x0000face);
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nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
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nvkm_wo32(chan->inst, 0x048, lower_32_bits(args->ioffset));
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nvkm_wo32(chan->inst, 0x04c, upper_32_bits(args->ioffset) |
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(order_base_2(args->ilength / 8) << 16));
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nvkm_wo32(chan->inst, 0x084, 0x20400000);
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nvkm_wo32(chan->inst, 0x094, 0x30000001);
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nvkm_wo32(chan->inst, 0x0ac, 0x00020000);
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nvkm_wo32(chan->inst, 0x0e4, 0x00000000);
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nvkm_wo32(chan->inst, 0x0e8, 0);
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nvkm_wo32(chan->inst, 0x0f4, 0x00001000);
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nvkm_wo32(chan->inst, 0x0f8, 0x10003080);
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nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
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nvkm_wo32(chan->inst, 0x220, lower_32_bits(nvkm_memory_bar2(chan->mthd)));
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nvkm_wo32(chan->inst, 0x224, upper_32_bits(nvkm_memory_bar2(chan->mthd)));
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nvkm_done(chan->inst);
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->user);
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if (ret)
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return ret;
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, true, &chan->runl);
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if (ret)
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return ret;
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nvkm_kmap(chan->runl);
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nvkm_wo32(chan->runl, 0x00, 0x80030001);
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nvkm_wo32(chan->runl, 0x04, 1);
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nvkm_wo32(chan->runl, 0x08, 0);
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nvkm_wo32(chan->runl, 0x0c, 0x00000000);
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nvkm_wo32(chan->runl, 0x10, lower_32_bits(nvkm_memory_addr(chan->user)));
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nvkm_wo32(chan->runl, 0x14, upper_32_bits(nvkm_memory_addr(chan->user)));
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nvkm_wo32(chan->runl, 0x18, lower_32_bits(nvkm_memory_addr(chan->inst)));
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nvkm_wo32(chan->runl, 0x1c, upper_32_bits(nvkm_memory_addr(chan->inst)));
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nvkm_done(chan->runl);
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ret = nvkm_vmm_join(vmm, chan->inst);
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if (ret)
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return ret;
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chan->vmm = nvkm_vmm_ref(vmm);
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return 0;
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}
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static const struct nvkm_device_oclass
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ga102_chan_oclass = {
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.ctor = ga102_chan_new,
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};
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static int
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ga102_user_new(struct nvkm_device *device,
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const struct nvkm_oclass *oclass, void *argv, u32 argc, struct nvkm_object **pobject)
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{
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return tu102_fifo_user_new(oclass, argv, argc, pobject);
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}
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static const struct nvkm_device_oclass
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ga102_user_oclass = {
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.ctor = ga102_user_new,
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};
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static int
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ga102_fifo_sclass(struct nvkm_oclass *oclass, int index, const struct nvkm_device_oclass **class)
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{
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if (index == 0) {
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oclass->base = (struct nvkm_sclass) { -1, -1, VOLTA_USERMODE_A };
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*class = &ga102_user_oclass;
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return 0;
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} else
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if (index == 1) {
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oclass->base = (struct nvkm_sclass) { 0, 0, AMPERE_CHANNEL_GPFIFO_B };
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*class = &ga102_chan_oclass;
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return 0;
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}
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return 2;
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}
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static int
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ga102_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data)
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{
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switch (mthd) {
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case NV_DEVICE_HOST_CHANNELS: *data = 1; return 0;
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default:
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break;
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}
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return -ENOSYS;
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}
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static void *
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ga102_fifo_dtor(struct nvkm_engine *engine)
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{
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return ga102_fifo(engine);
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}
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static const struct nvkm_engine_func
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ga102_fifo = {
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.dtor = ga102_fifo_dtor,
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.info = ga102_fifo_info,
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.base.sclass = ga102_fifo_sclass,
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};
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int
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ga102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_fifo **pfifo)
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{
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struct ga102_fifo *fifo;
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if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_engine_ctor(&ga102_fifo, device, type, inst, true, &fifo->base.engine);
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*pfifo = &fifo->base;
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return 0;
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}
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