444 lines
11 KiB
C
444 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car Gen2 PHY driver
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*
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* Copyright (C) 2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded, Inc.
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/atomic.h>
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#include <linux/of_device.h>
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#define USBHS_LPSTS 0x02
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#define USBHS_UGCTRL 0x80
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#define USBHS_UGCTRL2 0x84
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#define USBHS_UGSTS 0x88 /* From technical update */
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/* Low Power Status register (LPSTS) */
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#define USBHS_LPSTS_SUSPM 0x4000
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/* USB General control register (UGCTRL) */
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#define USBHS_UGCTRL_CONNECT 0x00000004
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#define USBHS_UGCTRL_PLLRESET 0x00000001
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/* USB General control register 2 (UGCTRL2) */
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#define USBHS_UGCTRL2_USB2SEL 0x80000000
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#define USBHS_UGCTRL2_USB2SEL_PCI 0x00000000
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#define USBHS_UGCTRL2_USB2SEL_USB30 0x80000000
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#define USBHS_UGCTRL2_USB0SEL 0x00000030
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#define USBHS_UGCTRL2_USB0SEL_PCI 0x00000010
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#define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030
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#define USBHS_UGCTRL2_USB0SEL_USB20 0x00000010
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#define USBHS_UGCTRL2_USB0SEL_HS_USB20 0x00000020
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/* USB General status register (UGSTS) */
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#define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */
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#define PHYS_PER_CHANNEL 2
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struct rcar_gen2_phy {
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struct phy *phy;
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struct rcar_gen2_channel *channel;
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int number;
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u32 select_value;
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};
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struct rcar_gen2_channel {
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struct device_node *of_node;
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struct rcar_gen2_phy_driver *drv;
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struct rcar_gen2_phy phys[PHYS_PER_CHANNEL];
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int selected_phy;
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u32 select_mask;
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};
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struct rcar_gen2_phy_driver {
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void __iomem *base;
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struct clk *clk;
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spinlock_t lock;
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int num_channels;
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struct rcar_gen2_channel *channels;
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};
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struct rcar_gen2_phy_data {
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const struct phy_ops *gen2_phy_ops;
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const u32 (*select_value)[PHYS_PER_CHANNEL];
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const u32 num_channels;
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};
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static int rcar_gen2_phy_init(struct phy *p)
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{
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struct rcar_gen2_phy *phy = phy_get_drvdata(p);
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struct rcar_gen2_channel *channel = phy->channel;
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struct rcar_gen2_phy_driver *drv = channel->drv;
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unsigned long flags;
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u32 ugctrl2;
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/*
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* Try to acquire exclusive access to PHY. The first driver calling
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* phy_init() on a given channel wins, and all attempts to use another
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* PHY on this channel will fail until phy_exit() is called by the first
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* driver. Achieving this with cmpxcgh() should be SMP-safe.
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*/
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if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1)
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return -EBUSY;
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clk_prepare_enable(drv->clk);
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spin_lock_irqsave(&drv->lock, flags);
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ugctrl2 = readl(drv->base + USBHS_UGCTRL2);
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ugctrl2 &= ~channel->select_mask;
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ugctrl2 |= phy->select_value;
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writel(ugctrl2, drv->base + USBHS_UGCTRL2);
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spin_unlock_irqrestore(&drv->lock, flags);
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return 0;
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}
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static int rcar_gen2_phy_exit(struct phy *p)
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{
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struct rcar_gen2_phy *phy = phy_get_drvdata(p);
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struct rcar_gen2_channel *channel = phy->channel;
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clk_disable_unprepare(channel->drv->clk);
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channel->selected_phy = -1;
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return 0;
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}
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static int rcar_gen2_phy_power_on(struct phy *p)
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{
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struct rcar_gen2_phy *phy = phy_get_drvdata(p);
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struct rcar_gen2_phy_driver *drv = phy->channel->drv;
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void __iomem *base = drv->base;
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unsigned long flags;
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u32 value;
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int err = 0, i;
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/* Skip if it's not USBHS */
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if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
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return 0;
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spin_lock_irqsave(&drv->lock, flags);
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/* Power on USBHS PHY */
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value = readl(base + USBHS_UGCTRL);
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value &= ~USBHS_UGCTRL_PLLRESET;
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writel(value, base + USBHS_UGCTRL);
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value = readw(base + USBHS_LPSTS);
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value |= USBHS_LPSTS_SUSPM;
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writew(value, base + USBHS_LPSTS);
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for (i = 0; i < 20; i++) {
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value = readl(base + USBHS_UGSTS);
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if ((value & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
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value = readl(base + USBHS_UGCTRL);
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value |= USBHS_UGCTRL_CONNECT;
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writel(value, base + USBHS_UGCTRL);
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goto out;
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}
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udelay(1);
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}
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/* Timed out waiting for the PLL lock */
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err = -ETIMEDOUT;
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out:
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spin_unlock_irqrestore(&drv->lock, flags);
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return err;
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}
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static int rcar_gen2_phy_power_off(struct phy *p)
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{
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struct rcar_gen2_phy *phy = phy_get_drvdata(p);
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struct rcar_gen2_phy_driver *drv = phy->channel->drv;
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void __iomem *base = drv->base;
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unsigned long flags;
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u32 value;
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/* Skip if it's not USBHS */
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if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
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return 0;
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spin_lock_irqsave(&drv->lock, flags);
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/* Power off USBHS PHY */
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value = readl(base + USBHS_UGCTRL);
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value &= ~USBHS_UGCTRL_CONNECT;
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writel(value, base + USBHS_UGCTRL);
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value = readw(base + USBHS_LPSTS);
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value &= ~USBHS_LPSTS_SUSPM;
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writew(value, base + USBHS_LPSTS);
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value = readl(base + USBHS_UGCTRL);
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value |= USBHS_UGCTRL_PLLRESET;
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writel(value, base + USBHS_UGCTRL);
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spin_unlock_irqrestore(&drv->lock, flags);
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return 0;
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}
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static int rz_g1c_phy_power_on(struct phy *p)
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{
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struct rcar_gen2_phy *phy = phy_get_drvdata(p);
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struct rcar_gen2_phy_driver *drv = phy->channel->drv;
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void __iomem *base = drv->base;
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&drv->lock, flags);
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/* Power on USBHS PHY */
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value = readl(base + USBHS_UGCTRL);
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value &= ~USBHS_UGCTRL_PLLRESET;
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writel(value, base + USBHS_UGCTRL);
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/* As per the data sheet wait 340 micro sec for power stable */
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udelay(340);
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if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) {
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value = readw(base + USBHS_LPSTS);
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value |= USBHS_LPSTS_SUSPM;
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writew(value, base + USBHS_LPSTS);
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}
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spin_unlock_irqrestore(&drv->lock, flags);
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return 0;
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}
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static int rz_g1c_phy_power_off(struct phy *p)
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{
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struct rcar_gen2_phy *phy = phy_get_drvdata(p);
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struct rcar_gen2_phy_driver *drv = phy->channel->drv;
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void __iomem *base = drv->base;
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&drv->lock, flags);
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/* Power off USBHS PHY */
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if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) {
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value = readw(base + USBHS_LPSTS);
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value &= ~USBHS_LPSTS_SUSPM;
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writew(value, base + USBHS_LPSTS);
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}
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value = readl(base + USBHS_UGCTRL);
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value |= USBHS_UGCTRL_PLLRESET;
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writel(value, base + USBHS_UGCTRL);
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spin_unlock_irqrestore(&drv->lock, flags);
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return 0;
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}
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static const struct phy_ops rcar_gen2_phy_ops = {
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.init = rcar_gen2_phy_init,
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.exit = rcar_gen2_phy_exit,
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.power_on = rcar_gen2_phy_power_on,
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.power_off = rcar_gen2_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct phy_ops rz_g1c_phy_ops = {
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.init = rcar_gen2_phy_init,
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.exit = rcar_gen2_phy_exit,
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.power_on = rz_g1c_phy_power_on,
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.power_off = rz_g1c_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const u32 pci_select_value[][PHYS_PER_CHANNEL] = {
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[0] = { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB },
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[2] = { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 },
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};
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static const u32 usb20_select_value[][PHYS_PER_CHANNEL] = {
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{ USBHS_UGCTRL2_USB0SEL_USB20, USBHS_UGCTRL2_USB0SEL_HS_USB20 },
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};
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static const struct rcar_gen2_phy_data rcar_gen2_usb_phy_data = {
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.gen2_phy_ops = &rcar_gen2_phy_ops,
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.select_value = pci_select_value,
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.num_channels = ARRAY_SIZE(pci_select_value),
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};
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static const struct rcar_gen2_phy_data rz_g1c_usb_phy_data = {
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.gen2_phy_ops = &rz_g1c_phy_ops,
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.select_value = usb20_select_value,
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.num_channels = ARRAY_SIZE(usb20_select_value),
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};
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static const struct of_device_id rcar_gen2_phy_match_table[] = {
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{
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.compatible = "renesas,usb-phy-r8a77470",
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.data = &rz_g1c_usb_phy_data,
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},
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{
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.compatible = "renesas,usb-phy-r8a7790",
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.data = &rcar_gen2_usb_phy_data,
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},
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{
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.compatible = "renesas,usb-phy-r8a7791",
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.data = &rcar_gen2_usb_phy_data,
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},
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{
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.compatible = "renesas,usb-phy-r8a7794",
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.data = &rcar_gen2_usb_phy_data,
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},
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{
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.compatible = "renesas,rcar-gen2-usb-phy",
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.data = &rcar_gen2_usb_phy_data,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table);
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static struct phy *rcar_gen2_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct rcar_gen2_phy_driver *drv;
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struct device_node *np = args->np;
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int i;
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drv = dev_get_drvdata(dev);
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if (!drv)
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return ERR_PTR(-EINVAL);
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for (i = 0; i < drv->num_channels; i++) {
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if (np == drv->channels[i].of_node)
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break;
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}
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if (i >= drv->num_channels || args->args[0] >= 2)
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return ERR_PTR(-ENODEV);
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return drv->channels[i].phys[args->args[0]].phy;
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}
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static const u32 select_mask[] = {
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[0] = USBHS_UGCTRL2_USB0SEL,
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[2] = USBHS_UGCTRL2_USB2SEL,
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};
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static int rcar_gen2_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rcar_gen2_phy_driver *drv;
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struct phy_provider *provider;
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struct device_node *np;
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void __iomem *base;
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struct clk *clk;
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const struct rcar_gen2_phy_data *data;
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int i = 0;
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if (!dev->of_node) {
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dev_err(dev,
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"This driver is required to be instantiated from device tree\n");
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return -EINVAL;
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}
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clk = devm_clk_get(dev, "usbhs");
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if (IS_ERR(clk)) {
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dev_err(dev, "Can't get USBHS clock\n");
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return PTR_ERR(clk);
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}
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
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if (!drv)
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return -ENOMEM;
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spin_lock_init(&drv->lock);
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drv->clk = clk;
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drv->base = base;
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data = of_device_get_match_data(dev);
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if (!data)
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return -EINVAL;
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drv->num_channels = of_get_child_count(dev->of_node);
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drv->channels = devm_kcalloc(dev, drv->num_channels,
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sizeof(struct rcar_gen2_channel),
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GFP_KERNEL);
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if (!drv->channels)
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return -ENOMEM;
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for_each_child_of_node(dev->of_node, np) {
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struct rcar_gen2_channel *channel = drv->channels + i;
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u32 channel_num;
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int error, n;
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channel->of_node = np;
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channel->drv = drv;
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channel->selected_phy = -1;
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error = of_property_read_u32(np, "reg", &channel_num);
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if (error || channel_num >= data->num_channels) {
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dev_err(dev, "Invalid \"reg\" property\n");
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of_node_put(np);
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return error;
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}
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channel->select_mask = select_mask[channel_num];
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for (n = 0; n < PHYS_PER_CHANNEL; n++) {
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struct rcar_gen2_phy *phy = &channel->phys[n];
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phy->channel = channel;
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phy->number = n;
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phy->select_value = data->select_value[channel_num][n];
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phy->phy = devm_phy_create(dev, NULL,
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data->gen2_phy_ops);
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if (IS_ERR(phy->phy)) {
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dev_err(dev, "Failed to create PHY\n");
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of_node_put(np);
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return PTR_ERR(phy->phy);
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}
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phy_set_drvdata(phy->phy, phy);
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}
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i++;
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}
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provider = devm_of_phy_provider_register(dev, rcar_gen2_phy_xlate);
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if (IS_ERR(provider)) {
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dev_err(dev, "Failed to register PHY provider\n");
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return PTR_ERR(provider);
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}
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dev_set_drvdata(dev, drv);
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return 0;
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}
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static struct platform_driver rcar_gen2_phy_driver = {
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.driver = {
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.name = "phy_rcar_gen2",
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.of_match_table = rcar_gen2_phy_match_table,
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},
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.probe = rcar_gen2_phy_probe,
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};
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module_platform_driver(rcar_gen2_phy_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Renesas R-Car Gen2 PHY");
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MODULE_AUTHOR("Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>");
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