137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+
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* Microchip Sparx5 SerDes driver
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*
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* Copyright (c) 2020 Microchip Technology Inc.
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*/
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#ifndef _SPARX5_SERDES_H_
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#define _SPARX5_SERDES_H_
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#include "sparx5_serdes_regs.h"
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#define SPX5_SERDES_MAX 33
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enum sparx5_serdes_type {
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SPX5_SDT_6G = 6,
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SPX5_SDT_10G = 10,
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SPX5_SDT_25G = 25,
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};
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enum sparx5_serdes_mode {
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SPX5_SD_MODE_NONE,
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SPX5_SD_MODE_2G5,
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SPX5_SD_MODE_QSGMII,
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SPX5_SD_MODE_100FX,
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SPX5_SD_MODE_1000BASEX,
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SPX5_SD_MODE_SFI,
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};
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struct sparx5_serdes_private {
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struct device *dev;
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void __iomem *regs[NUM_TARGETS];
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struct phy *phys[SPX5_SERDES_MAX];
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bool cmu_enabled;
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unsigned long coreclock;
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};
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struct sparx5_serdes_macro {
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struct sparx5_serdes_private *priv;
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u32 sidx;
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u32 stpidx;
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enum sparx5_serdes_type serdestype;
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enum sparx5_serdes_mode serdesmode;
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phy_interface_t portmode;
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int speed;
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enum phy_media media;
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};
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/* Read, Write and modify registers content.
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* The register definition macros start at the id
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*/
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static inline void __iomem *sdx5_addr(void __iomem *base[],
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int id, int tinst, int tcnt,
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int gbase, int ginst,
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int gcnt, int gwidth,
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int raddr, int rinst,
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int rcnt, int rwidth)
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{
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WARN_ON((tinst) >= tcnt);
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WARN_ON((ginst) >= gcnt);
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WARN_ON((rinst) >= rcnt);
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return base[id + (tinst)] +
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gbase + ((ginst) * gwidth) +
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raddr + ((rinst) * rwidth);
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}
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static inline void __iomem *sdx5_inst_baseaddr(void __iomem *base,
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int gbase, int ginst,
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int gcnt, int gwidth,
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int raddr, int rinst,
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int rcnt, int rwidth)
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{
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WARN_ON((ginst) >= gcnt);
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WARN_ON((rinst) >= rcnt);
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return base +
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gbase + ((ginst) * gwidth) +
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raddr + ((rinst) * rwidth);
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}
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static inline void sdx5_rmw(u32 val, u32 mask, struct sparx5_serdes_private *priv,
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int id, int tinst, int tcnt,
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int gbase, int ginst, int gcnt, int gwidth,
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int raddr, int rinst, int rcnt, int rwidth)
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{
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u32 nval;
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void __iomem *addr =
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sdx5_addr(priv->regs, id, tinst, tcnt,
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gbase, ginst, gcnt, gwidth,
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raddr, rinst, rcnt, rwidth);
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nval = readl(addr);
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nval = (nval & ~mask) | (val & mask);
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writel(nval, addr);
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}
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static inline void sdx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
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int id, int tinst, int tcnt,
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int gbase, int ginst, int gcnt, int gwidth,
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int raddr, int rinst, int rcnt, int rwidth)
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{
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u32 nval;
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void __iomem *addr =
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sdx5_inst_baseaddr(iomem,
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gbase, ginst, gcnt, gwidth,
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raddr, rinst, rcnt, rwidth);
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nval = readl(addr);
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nval = (nval & ~mask) | (val & mask);
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writel(nval, addr);
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}
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static inline void sdx5_rmw_addr(u32 val, u32 mask, void __iomem *addr)
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{
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u32 nval;
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nval = readl(addr);
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nval = (nval & ~mask) | (val & mask);
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writel(nval, addr);
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}
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static inline void __iomem *sdx5_inst_get(struct sparx5_serdes_private *priv,
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int id, int tinst)
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{
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return priv->regs[id + tinst];
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}
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static inline void __iomem *sdx5_inst_addr(void __iomem *iomem,
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int id, int tinst, int tcnt,
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int gbase,
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int ginst, int gcnt, int gwidth,
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int raddr,
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int rinst, int rcnt, int rwidth)
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{
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return sdx5_inst_baseaddr(iomem, gbase, ginst, gcnt, gwidth,
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raddr, rinst, rcnt, rwidth);
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}
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#endif /* _SPARX5_SERDES_REGS_H_ */
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