203 lines
5.9 KiB
C
203 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek DisplayPort PHY driver
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*
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* Copyright (c) 2022, BayLibre Inc.
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* Copyright (c) 2022, MediaTek Inc.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define PHY_OFFSET 0x1000
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#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14)
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#define TPLL_SSC_EN BIT(3)
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#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C)
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#define BIT_RATE_RBR 0
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#define BIT_RATE_HBR 1
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#define BIT_RATE_HBR2 2
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#define BIT_RATE_HBR3 3
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#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38)
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#define DP_GLB_SW_RST_PHYD BIT(0)
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#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138)
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#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238)
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#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338)
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#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438)
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#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4)
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#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12))
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#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19)
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#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29)
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#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
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#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3)
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#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9)
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#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21))
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#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29)
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#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
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#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5))
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#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12)
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#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
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XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
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#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0
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#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10)
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#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19)
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#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28)
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#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
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#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0
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#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9)
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#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18)
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#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0
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#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
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#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3)
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#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0
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#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
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XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
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struct mtk_dp_phy {
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struct regmap *regs;
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};
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static int mtk_dp_phy_init(struct phy *phy)
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{
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struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
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static const u32 driving_params[] = {
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DRIVING_PARAM_3_DEFAULT,
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DRIVING_PARAM_4_DEFAULT,
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DRIVING_PARAM_5_DEFAULT,
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DRIVING_PARAM_6_DEFAULT,
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DRIVING_PARAM_7_DEFAULT,
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DRIVING_PARAM_8_DEFAULT
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};
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regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3,
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driving_params, ARRAY_SIZE(driving_params));
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regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3,
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driving_params, ARRAY_SIZE(driving_params));
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regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3,
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driving_params, ARRAY_SIZE(driving_params));
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regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3,
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driving_params, ARRAY_SIZE(driving_params));
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return 0;
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}
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static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
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{
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struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
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u32 val;
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if (opts->dp.set_rate) {
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switch (opts->dp.link_rate) {
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default:
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dev_err(&phy->dev,
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"Implementation error, unknown linkrate %x\n",
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opts->dp.link_rate);
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return -EINVAL;
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case 1620:
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val = BIT_RATE_RBR;
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break;
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case 2700:
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val = BIT_RATE_HBR;
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break;
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case 5400:
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val = BIT_RATE_HBR2;
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break;
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case 8100:
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val = BIT_RATE_HBR3;
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break;
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}
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regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val);
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}
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regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
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TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
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return 0;
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}
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static int mtk_dp_phy_reset(struct phy *phy)
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{
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struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
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regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST,
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DP_GLB_SW_RST_PHYD, 0);
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usleep_range(50, 200);
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regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST,
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DP_GLB_SW_RST_PHYD, 1);
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return 0;
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}
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static const struct phy_ops mtk_dp_phy_dev_ops = {
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.init = mtk_dp_phy_init,
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.configure = mtk_dp_phy_configure,
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.reset = mtk_dp_phy_reset,
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.owner = THIS_MODULE,
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};
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static int mtk_dp_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_dp_phy *dp_phy;
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struct phy *phy;
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struct regmap *regs;
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regs = *(struct regmap **)dev->platform_data;
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if (!regs)
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return dev_err_probe(dev, -EINVAL,
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"No data passed, requires struct regmap**\n");
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dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL);
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if (!dp_phy)
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return -ENOMEM;
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dp_phy->regs = regs;
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phy = devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops);
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if (IS_ERR(phy))
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return dev_err_probe(dev, PTR_ERR(phy),
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"Failed to create DP PHY\n");
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phy_set_drvdata(phy, dp_phy);
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if (!dev->of_node)
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phy_create_lookup(phy, "dp", dev_name(dev));
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return 0;
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}
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static struct platform_driver mtk_dp_phy_driver = {
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.probe = mtk_dp_phy_probe,
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.driver = {
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.name = "mediatek-dp-phy",
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},
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};
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module_platform_driver(mtk_dp_phy_driver);
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MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com>");
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MODULE_DESCRIPTION("MediaTek DP PHY Driver");
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MODULE_LICENSE("GPL");
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