161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson8, Meson8b and Meson8m2 HDMI TX PHY.
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*
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* Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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/*
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* Unfortunately there is no detailed documentation available for the
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* HHI_HDMI_PHY_CNTL0 register. CTL0 and CTL1 is all we know about.
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* Magic register values in the driver below are taken from the vendor
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* BSP / kernel.
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*/
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#define HHI_HDMI_PHY_CNTL0 0x3a0
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#define HHI_HDMI_PHY_CNTL0_HDMI_CTL1 GENMASK(31, 16)
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#define HHI_HDMI_PHY_CNTL0_HDMI_CTL0 GENMASK(15, 0)
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#define HHI_HDMI_PHY_CNTL1 0x3a4
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#define HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE BIT(1)
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#define HHI_HDMI_PHY_CNTL1_SOFT_RESET BIT(0)
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#define HHI_HDMI_PHY_CNTL2 0x3a8
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struct phy_meson8_hdmi_tx_priv {
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struct regmap *hhi;
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struct clk *tmds_clk;
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};
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static int phy_meson8_hdmi_tx_init(struct phy *phy)
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{
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struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
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return clk_prepare_enable(priv->tmds_clk);
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}
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static int phy_meson8_hdmi_tx_exit(struct phy *phy)
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{
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struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
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clk_disable_unprepare(priv->tmds_clk);
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return 0;
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}
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static int phy_meson8_hdmi_tx_power_on(struct phy *phy)
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{
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struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
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unsigned int i;
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u16 hdmi_ctl0;
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if (clk_get_rate(priv->tmds_clk) >= 2970UL * 1000 * 1000)
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hdmi_ctl0 = 0x1e8b;
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else
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hdmi_ctl0 = 0x4d0b;
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0,
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FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x08c3) |
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FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, hdmi_ctl0));
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x0);
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/* Reset three times, just like the vendor driver does */
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for (i = 0; i < 3; i++) {
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1,
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HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE |
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HHI_HDMI_PHY_CNTL1_SOFT_RESET);
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usleep_range(1000, 2000);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1,
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HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE);
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usleep_range(1000, 2000);
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}
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return 0;
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}
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static int phy_meson8_hdmi_tx_power_off(struct phy *phy)
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{
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struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0,
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FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x0841) |
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FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, 0x8d00));
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return 0;
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}
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static const struct phy_ops phy_meson8_hdmi_tx_ops = {
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.init = phy_meson8_hdmi_tx_init,
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.exit = phy_meson8_hdmi_tx_exit,
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.power_on = phy_meson8_hdmi_tx_power_on,
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.power_off = phy_meson8_hdmi_tx_power_off,
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.owner = THIS_MODULE,
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};
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static int phy_meson8_hdmi_tx_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct phy_meson8_hdmi_tx_priv *priv;
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struct phy_provider *phy_provider;
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struct resource *res;
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struct phy *phy;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EINVAL;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->hhi = syscon_node_to_regmap(np->parent);
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if (IS_ERR(priv->hhi))
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return PTR_ERR(priv->hhi);
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priv->tmds_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(priv->tmds_clk))
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return PTR_ERR(priv->tmds_clk);
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phy = devm_phy_create(&pdev->dev, np, &phy_meson8_hdmi_tx_ops);
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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phy_set_drvdata(phy, priv);
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phy_provider = devm_of_phy_provider_register(&pdev->dev,
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of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id phy_meson8_hdmi_tx_of_match[] = {
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{ .compatible = "amlogic,meson8-hdmi-tx-phy" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, phy_meson8_hdmi_tx_of_match);
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static struct platform_driver phy_meson8_hdmi_tx_driver = {
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.probe = phy_meson8_hdmi_tx_probe,
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.driver = {
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.name = "phy-meson8-hdmi-tx",
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.of_match_table = phy_meson8_hdmi_tx_of_match,
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},
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};
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module_platform_driver(phy_meson8_hdmi_tx_driver);
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Meson8, Meson8b and Meson8m2 HDMI TX PHY driver");
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MODULE_LICENSE("GPL v2");
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