136 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			136 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/* SPDX-License-Identifier: GPL-2.0-only
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 *
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 * Copyright (c) 2021, MediaTek Inc.
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 * Copyright (c) 2021-2022, Intel Corporation.
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 *
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 * Authors:
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 *  Haijun Liu <haijun.liu@mediatek.com>
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 *  Moises Veleta <moises.veleta@intel.com>
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 *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
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 *
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 * Contributors:
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 *  Amir Hanania <amir.hanania@intel.com>
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 *  Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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 *  Chandrashekar Devegowda <chandrashekar.devegowda@intel.com>
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 *  Eliot Lee <eliot.lee@intel.com>
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 */
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#ifndef __T7XX_PORT_H__
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#define __T7XX_PORT_H__
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/sched.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <linux/wwan.h>
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#include "t7xx_hif_cldma.h"
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#include "t7xx_pci.h"
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#define PORT_CH_ID_MASK		GENMASK(7, 0)
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/* Channel ID and Message ID definitions.
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 * The channel number consists of peer_id(15:12) , channel_id(11:0)
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 * peer_id:
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 * 0:reserved, 1: to sAP, 2: to MD
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 */
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enum port_ch {
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	/* to MD */
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	PORT_CH_CONTROL_RX = 0x2000,
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	PORT_CH_CONTROL_TX = 0x2001,
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	PORT_CH_UART1_RX = 0x2006,	/* META */
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	PORT_CH_UART1_TX = 0x2008,
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	PORT_CH_UART2_RX = 0x200a,	/* AT */
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	PORT_CH_UART2_TX = 0x200c,
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	PORT_CH_MD_LOG_RX = 0x202a,	/* MD logging */
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	PORT_CH_MD_LOG_TX = 0x202b,
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	PORT_CH_LB_IT_RX = 0x203e,	/* Loop back test */
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	PORT_CH_LB_IT_TX = 0x203f,
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	PORT_CH_STATUS_RX = 0x2043,	/* Status events */
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	PORT_CH_MIPC_RX = 0x20ce,	/* MIPC */
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	PORT_CH_MIPC_TX = 0x20cf,
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	PORT_CH_MBIM_RX = 0x20d0,
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	PORT_CH_MBIM_TX = 0x20d1,
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	PORT_CH_DSS0_RX = 0x20d2,
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	PORT_CH_DSS0_TX = 0x20d3,
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	PORT_CH_DSS1_RX = 0x20d4,
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	PORT_CH_DSS1_TX = 0x20d5,
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	PORT_CH_DSS2_RX = 0x20d6,
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	PORT_CH_DSS2_TX = 0x20d7,
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	PORT_CH_DSS3_RX = 0x20d8,
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	PORT_CH_DSS3_TX = 0x20d9,
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	PORT_CH_DSS4_RX = 0x20da,
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	PORT_CH_DSS4_TX = 0x20db,
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	PORT_CH_DSS5_RX = 0x20dc,
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	PORT_CH_DSS5_TX = 0x20dd,
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	PORT_CH_DSS6_RX = 0x20de,
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	PORT_CH_DSS6_TX = 0x20df,
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	PORT_CH_DSS7_RX = 0x20e0,
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	PORT_CH_DSS7_TX = 0x20e1,
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};
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struct t7xx_port;
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struct port_ops {
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	int (*init)(struct t7xx_port *port);
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	int (*recv_skb)(struct t7xx_port *port, struct sk_buff *skb);
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	void (*md_state_notify)(struct t7xx_port *port, unsigned int md_state);
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	void (*uninit)(struct t7xx_port *port);
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	int (*enable_chl)(struct t7xx_port *port);
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	int (*disable_chl)(struct t7xx_port *port);
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};
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struct t7xx_port_conf {
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	enum port_ch		tx_ch;
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	enum port_ch		rx_ch;
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	unsigned char		txq_index;
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	unsigned char		rxq_index;
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	unsigned char		txq_exp_index;
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	unsigned char		rxq_exp_index;
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	enum cldma_id		path_id;
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	struct port_ops		*ops;
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	char			*name;
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	enum wwan_port_type	port_type;
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};
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struct t7xx_port {
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	/* Members not initialized in definition */
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	const struct t7xx_port_conf	*port_conf;
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	struct wwan_port		*wwan_port;
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	struct t7xx_pci_dev		*t7xx_dev;
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	struct device			*dev;
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	u16				seq_nums[2];	/* TX/RX sequence numbers */
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	atomic_t			usage_cnt;
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	struct				list_head entry;
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	struct				list_head queue_entry;
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	/* TX and RX flows are asymmetric since ports are multiplexed on
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	 * queues.
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	 *
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	 * TX: data blocks are sent directly to a queue. Each port
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	 * does not maintain a TX list; instead, they only provide
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	 * a wait_queue_head for blocking writes.
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	 *
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	 * RX: Each port uses a RX list to hold packets,
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	 * allowing the modem to dispatch RX packet as quickly as possible.
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	 */
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	struct sk_buff_head		rx_skb_list;
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	spinlock_t			port_update_lock; /* Protects port configuration */
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	wait_queue_head_t		rx_wq;
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	int				rx_length_th;
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	bool				chan_enable;
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	struct task_struct		*thread;
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};
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struct sk_buff *t7xx_port_alloc_skb(int payload);
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struct sk_buff *t7xx_ctrl_alloc_skb(int payload);
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int t7xx_port_enqueue_skb(struct t7xx_port *port, struct sk_buff *skb);
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int t7xx_port_send_skb(struct t7xx_port *port, struct sk_buff *skb, unsigned int pkt_header,
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		       unsigned int ex_msg);
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int t7xx_port_send_ctl_skb(struct t7xx_port *port, struct sk_buff *skb, unsigned int msg,
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			   unsigned int ex_msg);
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#endif /* __T7XX_PORT_H__ */
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