130 lines
3.1 KiB
C
130 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Altera Corporation. All rights reserved
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "clk.h"
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#define CLK_MGR_FREE_SHIFT 16
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#define CLK_MGR_FREE_MASK 0x7
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#define SOCFPGA_MPU_FREE_CLK "mpu_free_clk"
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#define SOCFPGA_NOC_FREE_CLK "noc_free_clk"
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#define SOCFPGA_SDMMC_FREE_CLK "sdmmc_free_clk"
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#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
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static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
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u32 div;
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if (socfpgaclk->fixed_div) {
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div = socfpgaclk->fixed_div;
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} else if (socfpgaclk->div_reg) {
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div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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div &= GENMASK(socfpgaclk->width - 1, 0);
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div += 1;
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} else {
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div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
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}
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return parent_rate / div;
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}
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static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
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u32 clk_src;
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const char *name = clk_hw_get_name(hwclk);
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clk_src = readl(socfpgaclk->hw.reg);
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if (streq(name, SOCFPGA_MPU_FREE_CLK) ||
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streq(name, SOCFPGA_NOC_FREE_CLK) ||
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streq(name, SOCFPGA_SDMMC_FREE_CLK))
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return (clk_src >> CLK_MGR_FREE_SHIFT) &
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CLK_MGR_FREE_MASK;
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else
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return 0;
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}
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static const struct clk_ops periclk_ops = {
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.recalc_rate = clk_periclk_recalc_rate,
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.get_parent = clk_periclk_get_parent,
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};
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static __init void __socfpga_periph_init(struct device_node *node,
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const struct clk_ops *ops)
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{
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u32 reg;
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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int rc;
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u32 fixed_div;
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u32 div_reg[3];
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of_property_read_u32(node, "reg", ®);
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return;
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periph_clk->hw.reg = clk_mgr_a10_base_addr + reg;
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rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
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if (!rc) {
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periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
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periph_clk->shift = div_reg[1];
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periph_clk->width = div_reg[2];
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} else {
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periph_clk->div_reg = NULL;
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}
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rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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if (rc)
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periph_clk->fixed_div = 0;
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else
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periph_clk->fixed_div = fixed_div;
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
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init.parent_names = parent_name;
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periph_clk->hw.hw.init = &init;
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hw_clk = &periph_clk->hw.hw;
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if (clk_hw_register(NULL, hw_clk)) {
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kfree(periph_clk);
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return;
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}
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rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
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if (rc < 0) {
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pr_err("Could not register clock provider for node:%s\n",
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clk_name);
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goto err_clk;
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}
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return;
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err_clk:
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clk_hw_unregister(hw_clk);
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}
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void __init socfpga_a10_periph_init(struct device_node *node)
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{
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__socfpga_periph_init(node, &periclk_ops);
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}
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