242 lines
6.3 KiB
C
242 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "stratix10-clk.h"
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#include "clk.h"
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#define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
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#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
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#define SOCFPGA_EMAC0_CLK "emac0_clk"
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#define SOCFPGA_EMAC1_CLK "emac1_clk"
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#define SOCFPGA_EMAC2_CLK "emac2_clk"
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#define AGILEX_BYPASS_OFFSET 0xC
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#define STRATIX10_BYPASS_OFFSET 0x2C
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#define BOOTCLK_BYPASS 2
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static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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if (socfpgaclk->fixed_div) {
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div = socfpgaclk->fixed_div;
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} else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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}
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return parent_rate / div;
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}
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static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div, val;
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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div = div ? 4 : 1;
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return parent_rate / div;
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}
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static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 mask, second_bypass;
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u8 parent = 0;
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const char *name = clk_hw_get_name(hwclk);
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if (socfpgaclk->bypass_reg) {
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mask = (0x1 << socfpgaclk->bypass_shift);
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parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
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socfpgaclk->bypass_shift);
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}
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if (streq(name, SOCFPGA_EMAC0_CLK) ||
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streq(name, SOCFPGA_EMAC1_CLK) ||
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streq(name, SOCFPGA_EMAC2_CLK)) {
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second_bypass = readl(socfpgaclk->bypass_reg -
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STRATIX10_BYPASS_OFFSET);
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/* EMACA bypass to bootclk @0xB0 offset */
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if (second_bypass & 0x1)
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if (parent == 0) /* only applicable if parent is maca */
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parent = BOOTCLK_BYPASS;
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if (second_bypass & 0x2)
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if (parent == 1) /* only applicable if parent is macb */
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parent = BOOTCLK_BYPASS;
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}
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return parent;
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}
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static u8 socfpga_agilex_gate_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 mask, second_bypass;
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u8 parent = 0;
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const char *name = clk_hw_get_name(hwclk);
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if (socfpgaclk->bypass_reg) {
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mask = (0x1 << socfpgaclk->bypass_shift);
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parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
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socfpgaclk->bypass_shift);
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}
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if (streq(name, SOCFPGA_EMAC0_CLK) ||
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streq(name, SOCFPGA_EMAC1_CLK) ||
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streq(name, SOCFPGA_EMAC2_CLK)) {
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second_bypass = readl(socfpgaclk->bypass_reg -
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AGILEX_BYPASS_OFFSET);
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/* EMACA bypass to bootclk @0x88 offset */
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if (second_bypass & 0x1)
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if (parent == 0) /* only applicable if parent is maca */
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parent = BOOTCLK_BYPASS;
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if (second_bypass & 0x2)
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if (parent == 1) /* only applicable if parent is macb */
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parent = BOOTCLK_BYPASS;
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}
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return parent;
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}
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static struct clk_ops gateclk_ops = {
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.recalc_rate = socfpga_gate_clk_recalc_rate,
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.get_parent = socfpga_gate_get_parent,
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};
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static const struct clk_ops agilex_gateclk_ops = {
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.recalc_rate = socfpga_gate_clk_recalc_rate,
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.get_parent = socfpga_agilex_gate_get_parent,
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};
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static const struct clk_ops dbgclk_ops = {
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.recalc_rate = socfpga_dbg_clk_recalc_rate,
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.get_parent = socfpga_gate_get_parent,
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};
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struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
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{
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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const char *parent_name = clks->parent_name;
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int ret;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (!socfpga_clk)
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return NULL;
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socfpga_clk->hw.reg = regbase + clks->gate_reg;
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socfpga_clk->hw.bit_idx = clks->gate_idx;
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gateclk_ops.enable = clk_gate_ops.enable;
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gateclk_ops.disable = clk_gate_ops.disable;
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socfpga_clk->fixed_div = clks->fixed_div;
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if (clks->div_reg)
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socfpga_clk->div_reg = regbase + clks->div_reg;
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else
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socfpga_clk->div_reg = NULL;
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socfpga_clk->width = clks->div_width;
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socfpga_clk->shift = clks->div_offset;
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if (clks->bypass_reg)
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socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
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else
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socfpga_clk->bypass_reg = NULL;
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socfpga_clk->bypass_shift = clks->bypass_shift;
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if (streq(clks->name, "cs_pdbg_clk"))
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init.ops = &dbgclk_ops;
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else
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init.ops = &gateclk_ops;
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init.name = clks->name;
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init.flags = clks->flags;
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init.num_parents = clks->num_parents;
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init.parent_names = parent_name ? &parent_name : NULL;
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if (init.parent_names == NULL)
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init.parent_data = clks->parent_data;
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socfpga_clk->hw.hw.init = &init;
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hw_clk = &socfpga_clk->hw.hw;
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ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
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if (ret) {
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kfree(socfpga_clk);
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return ERR_PTR(ret);
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}
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return hw_clk;
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}
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struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
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{
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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const char *parent_name = clks->parent_name;
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int ret;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (!socfpga_clk)
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return NULL;
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socfpga_clk->hw.reg = regbase + clks->gate_reg;
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socfpga_clk->hw.bit_idx = clks->gate_idx;
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gateclk_ops.enable = clk_gate_ops.enable;
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gateclk_ops.disable = clk_gate_ops.disable;
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socfpga_clk->fixed_div = clks->fixed_div;
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if (clks->div_reg)
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socfpga_clk->div_reg = regbase + clks->div_reg;
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else
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socfpga_clk->div_reg = NULL;
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socfpga_clk->width = clks->div_width;
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socfpga_clk->shift = clks->div_offset;
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if (clks->bypass_reg)
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socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
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else
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socfpga_clk->bypass_reg = NULL;
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socfpga_clk->bypass_shift = clks->bypass_shift;
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if (streq(clks->name, "cs_pdbg_clk"))
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init.ops = &dbgclk_ops;
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else
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init.ops = &agilex_gateclk_ops;
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init.name = clks->name;
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init.flags = clks->flags;
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init.num_parents = clks->num_parents;
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init.parent_names = parent_name ? &parent_name : NULL;
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if (init.parent_names == NULL)
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init.parent_data = clks->parent_data;
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socfpga_clk->hw.hw.init = &init;
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hw_clk = &socfpga_clk->hw.hw;
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ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
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if (ret) {
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kfree(socfpga_clk);
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return ERR_PTR(ret);
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}
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return hw_clk;
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}
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