73 lines
1.7 KiB
YAML
73 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip rk3506 Family Clock and Reset Control Module
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maintainers:
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- Finley Xiao <finley.xiao@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |
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The RK3506 clock controller generates the clock and also implements a reset
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controller for SoC peripherals. For example it provides SCLK_UART2 and
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PCLK_UART2, as well as SRST_P_UART2 and SRST_UART2 for the second UART
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module.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clock and reset IDs
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are defined as preprocessor macros in dt-binding headers.
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properties:
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compatible:
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enum:
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- rockchip,rk3506-cru
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- rockchip,rk3506-grf-cru
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: xin24m
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- const: xin32k
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assigned-clocks: true
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assigned-clock-rates: true
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: >
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phandle to the syscon managing the "general register files". It is used
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for GRF muxes, if missing any muxes present in the GRF will not be
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available.
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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cru: clock-controller@ff9a0000 {
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compatible = "rockchip,rk3506-cru";
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reg = <0xff9a0000 0x20000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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