162 lines
4.4 KiB
JSON
162 lines
4.4 KiB
JSON
[
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
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"ArchStdEvent": "L1D_TLB",
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"BriefDescription": "L1D TLB access"
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},
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{
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"PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",
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"ArchStdEvent": "L1I_TLB"
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},
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{
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"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",
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"EventCode": "0x34",
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"EventName": "L2D_TLB_ACCESS",
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"BriefDescription": "L2D TLB access"
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},
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{
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"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
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"EventCode": "0x35",
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"EventName": "L2I_TLB_ACCESS",
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"BriefDescription": "L2I TLB access"
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},
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{
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"PublicDescription": "Branch target buffer misprediction",
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"EventCode": "0x102",
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"EventName": "BTB_MIS_PRED",
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"BriefDescription": "BTB misprediction"
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},
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{
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"PublicDescription": "ITB miss",
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"EventCode": "0x103",
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"EventName": "ITB_MISS",
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"BriefDescription": "ITB miss"
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},
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{
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"PublicDescription": "DTB miss",
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"EventCode": "0x104",
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"EventName": "DTB_MISS",
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"BriefDescription": "DTB miss"
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},
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{
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"PublicDescription": "Level 1 data cache late miss",
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"EventCode": "0x105",
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"EventName": "L1D_CACHE_LATE_MISS",
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"BriefDescription": "L1D cache late miss"
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},
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{
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"PublicDescription": "Level 1 data cache prefetch request",
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"EventCode": "0x106",
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"EventName": "L1D_CACHE_PREFETCH",
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"BriefDescription": "L1D cache prefetch"
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},
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{
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"PublicDescription": "Level 2 data cache prefetch request",
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"EventCode": "0x107",
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"EventName": "L2D_CACHE_PREFETCH",
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"BriefDescription": "L2D cache prefetch"
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},
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{
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"PublicDescription": "Level 1 stage 2 TLB refill",
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"EventCode": "0x111",
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"EventName": "L1_STAGE2_TLB_REFILL",
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"BriefDescription": "L1 stage 2 TLB refill"
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},
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{
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"PublicDescription": "Page walk cache level-0 stage-1 hit",
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"EventCode": "0x112",
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"EventName": "PAGE_WALK_L0_STAGE1_HIT",
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"BriefDescription": "Page walk, L0 stage-1 hit"
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},
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{
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"PublicDescription": "Page walk cache level-1 stage-1 hit",
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"EventCode": "0x113",
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"EventName": "PAGE_WALK_L1_STAGE1_HIT",
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"BriefDescription": "Page walk, L1 stage-1 hit"
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},
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{
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"PublicDescription": "Page walk cache level-2 stage-1 hit",
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"EventCode": "0x114",
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"EventName": "PAGE_WALK_L2_STAGE1_HIT",
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"BriefDescription": "Page walk, L2 stage-1 hit"
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},
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{
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"PublicDescription": "Page walk cache level-1 stage-2 hit",
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"EventCode": "0x115",
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"EventName": "PAGE_WALK_L1_STAGE2_HIT",
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"BriefDescription": "Page walk, L1 stage-2 hit"
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},
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{
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"PublicDescription": "Page walk cache level-2 stage-2 hit",
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"EventCode": "0x116",
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"EventName": "PAGE_WALK_L2_STAGE2_HIT",
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"BriefDescription": "Page walk, L2 stage-2 hit"
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}
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]
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