557 lines
9.3 KiB
ArmAsm
557 lines
9.3 KiB
ArmAsm
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2015-2019 ARM Limited.
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// Original author: Dave Martin <Dave.Martin@arm.com>
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//
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// Simple Scalable Vector Extension context switch test
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// Repeatedly writes unique test patterns into each SVE register
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// and reads them back to verify integrity.
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//
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// for x in `seq 1 NR_CPUS`; do sve-test & pids=$pids\ $! ; done
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// (leave it running for as long as you want...)
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// kill $pids
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#include <asm/unistd.h>
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#include "assembler.h"
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#include "asm-offsets.h"
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#include "sme-inst.h"
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#define NZR 32
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#define NPR 16
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#define MAXVL_B (2048 / 8)
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.arch_extension sve
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.macro _sve_ldr_v zt, xn
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ldr z\zt, [x\xn]
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.endm
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.macro _sve_str_v zt, xn
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str z\zt, [x\xn]
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.endm
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.macro _sve_ldr_p pt, xn
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ldr p\pt, [x\xn]
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.endm
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.macro _sve_str_p pt, xn
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str p\pt, [x\xn]
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.endm
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// Generate accessor functions to read/write programmatically selected
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// SVE registers.
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// x0 is the register index to access
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// x1 is the memory address to read from (getz,setp) or store to (setz,setp)
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// All clobber x0-x2
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define_accessor setz, NZR, _sve_ldr_v
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define_accessor getz, NZR, _sve_str_v
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define_accessor setp, NPR, _sve_ldr_p
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define_accessor getp, NPR, _sve_str_p
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// Declare some storate space to shadow the SVE register contents:
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.pushsection .text
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.data
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.align 4
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zref:
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.space MAXVL_B * NZR
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pref:
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.space MAXVL_B / 8 * NPR
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ffrref:
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.space MAXVL_B / 8
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scratch:
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.space MAXVL_B
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.popsection
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// Generate a test pattern for storage in SVE registers
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// x0: pid (16 bits)
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// x1: register number (6 bits)
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// x2: generation (4 bits)
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// These values are used to constuct a 32-bit pattern that is repeated in the
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// scratch buffer as many times as will fit:
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// bits 31:28 generation number (increments once per test_loop)
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// bits 27:22 32-bit lane index
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// bits 21:16 register number
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// bits 15: 0 pid
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function pattern
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orr w1, w0, w1, lsl #16
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orr w2, w1, w2, lsl #28
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ldr x0, =scratch
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mov w1, #MAXVL_B / 4
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0: str w2, [x0], #4
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add w2, w2, #(1 << 22)
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subs w1, w1, #1
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bne 0b
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ret
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endfunction
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// Get the address of shadow data for SVE Z-register Z<xn>
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.macro _adrz xd, xn, nrtmp
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ldr \xd, =zref
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rdvl x\nrtmp, #1
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madd \xd, x\nrtmp, \xn, \xd
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.endm
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// Get the address of shadow data for SVE P-register P<xn - NZR>
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.macro _adrp xd, xn, nrtmp
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ldr \xd, =pref
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rdvl x\nrtmp, #1
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lsr x\nrtmp, x\nrtmp, #3
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sub \xn, \xn, #NZR
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madd \xd, x\nrtmp, \xn, \xd
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.endm
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// Set up test pattern in a SVE Z-register
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// x0: pid
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// x1: register number
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// x2: generation
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function setup_zreg
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mov x4, x30
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mov x6, x1
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bl pattern
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_adrz x0, x6, 2
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mov x5, x0
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ldr x1, =scratch
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bl memcpy
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mov x0, x6
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mov x1, x5
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bl setz
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ret x4
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endfunction
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// Set up test pattern in a SVE P-register
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// x0: pid
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// x1: register number
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// x2: generation
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function setup_preg
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mov x4, x30
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mov x6, x1
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bl pattern
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_adrp x0, x6, 2
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mov x5, x0
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ldr x1, =scratch
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bl memcpy
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mov x0, x6
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mov x1, x5
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bl setp
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ret x4
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endfunction
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// Set up test pattern in the FFR
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// x0: pid
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// x2: generation
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//
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// We need to generate a canonical FFR value, which consists of a number of
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// low "1" bits, followed by a number of zeros. This gives us 17 unique values
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// per 16 bits of FFR, so we create a 4 bit signature out of the PID and
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// generation, and use that as the initial number of ones in the pattern.
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// We fill the upper lanes of FFR with zeros.
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// Beware: corrupts P0.
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function setup_ffr
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#ifndef SSVE
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mov x4, x30
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and w0, w0, #0x3
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bfi w0, w2, #2, #2
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mov w1, #1
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lsl w1, w1, w0
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sub w1, w1, #1
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ldr x0, =ffrref
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strh w1, [x0], 2
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rdvl x1, #1
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lsr x1, x1, #3
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sub x1, x1, #2
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bl memclr
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mov x0, #0
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ldr x1, =ffrref
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bl setp
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wrffr p0.b
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ret x4
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#else
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ret
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#endif
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endfunction
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// Trivial memory compare: compare x2 bytes starting at address x0 with
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// bytes starting at address x1.
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// Returns only if all bytes match; otherwise, the program is aborted.
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// Clobbers x0-x5.
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function memcmp
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cbz x2, 2f
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stp x0, x1, [sp, #-0x20]!
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str x2, [sp, #0x10]
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mov x5, #0
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0: ldrb w3, [x0, x5]
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ldrb w4, [x1, x5]
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add x5, x5, #1
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cmp w3, w4
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b.ne 1f
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subs x2, x2, #1
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b.ne 0b
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1: ldr x2, [sp, #0x10]
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ldp x0, x1, [sp], #0x20
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b.ne barf
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2: ret
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endfunction
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// Verify that a SVE Z-register matches its shadow in memory, else abort
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// x0: reg number
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// Clobbers x0-x7.
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function check_zreg
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mov x3, x30
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_adrz x5, x0, 6
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mov x4, x0
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ldr x7, =scratch
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mov x0, x7
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mov x1, x6
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bl memfill_ae
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mov x0, x4
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mov x1, x7
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bl getz
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mov x0, x5
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mov x1, x7
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mov x2, x6
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mov x30, x3
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b memcmp
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endfunction
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// Verify that a SVE P-register matches its shadow in memory, else abort
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// x0: reg number
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// Clobbers x0-x7.
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function check_preg
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mov x3, x30
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_adrp x5, x0, 6
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mov x4, x0
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ldr x7, =scratch
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mov x0, x7
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mov x1, x6
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bl memfill_ae
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mov x0, x4
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mov x1, x7
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bl getp
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mov x0, x5
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mov x1, x7
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mov x2, x6
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mov x30, x3
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b memcmp
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endfunction
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// Verify that the FFR matches its shadow in memory, else abort
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// Beware -- corrupts P0.
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// Clobbers x0-x5.
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function check_ffr
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#ifndef SSVE
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mov x3, x30
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ldr x4, =scratch
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rdvl x5, #1
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lsr x5, x5, #3
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mov x0, x4
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mov x1, x5
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bl memfill_ae
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rdffr p0.b
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mov x0, #0
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mov x1, x4
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bl getp
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ldr x0, =ffrref
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mov x1, x4
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mov x2, x5
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mov x30, x3
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b memcmp
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#else
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ret
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#endif
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endfunction
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// Any SVE register modified here can cause corruption in the main
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// thread -- but *only* the registers modified here.
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function irritator_handler
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// Increment the irritation signal count (x23):
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ldr x0, [x2, #ucontext_regs + 8 * 23]
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add x0, x0, #1
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str x0, [x2, #ucontext_regs + 8 * 23]
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// Corrupt some random Z-regs
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adr x0, .text + (irritator_handler - .text) / 16 * 16
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movi v0.8b, #1
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movi v9.16b, #2
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movi v31.8b, #3
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#ifndef SSVE
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// And P0
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rdffr p0.b
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// And FFR
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wrffr p15.b
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#endif
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ret
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endfunction
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function tickle_handler
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// Increment the signal count (x23):
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ldr x0, [x2, #ucontext_regs + 8 * 23]
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add x0, x0, #1
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str x0, [x2, #ucontext_regs + 8 * 23]
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ret
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endfunction
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function terminate_handler
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mov w21, w0
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mov x20, x2
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puts "Terminated by signal "
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mov w0, w21
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bl putdec
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puts ", no error, iterations="
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ldr x0, [x20, #ucontext_regs + 8 * 22]
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bl putdec
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puts ", signals="
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ldr x0, [x20, #ucontext_regs + 8 * 23]
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bl putdecn
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mov x0, #0
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mov x8, #__NR_exit
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svc #0
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endfunction
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// w0: signal number
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// x1: sa_action
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// w2: sa_flags
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// Clobbers x0-x6,x8
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function setsignal
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str x30, [sp, #-((sa_sz + 15) / 16 * 16 + 16)]!
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mov w4, w0
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mov x5, x1
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mov w6, w2
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add x0, sp, #16
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mov x1, #sa_sz
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bl memclr
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mov w0, w4
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add x1, sp, #16
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str w6, [x1, #sa_flags]
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str x5, [x1, #sa_handler]
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mov x2, #0
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mov x3, #sa_mask_sz
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mov x8, #__NR_rt_sigaction
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svc #0
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cbz w0, 1f
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puts "sigaction failure\n"
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b .Labort
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1: ldr x30, [sp], #((sa_sz + 15) / 16 * 16 + 16)
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ret
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endfunction
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// Main program entry point
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.globl _start
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function _start
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_start:
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mov x23, #0 // Irritation signal count
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mov w0, #SIGINT
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adr x1, terminate_handler
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mov w2, #SA_SIGINFO
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bl setsignal
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mov w0, #SIGTERM
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adr x1, terminate_handler
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mov w2, #SA_SIGINFO
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bl setsignal
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mov w0, #SIGUSR1
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adr x1, irritator_handler
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mov w2, #SA_SIGINFO
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orr w2, w2, #SA_NODEFER
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bl setsignal
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mov w0, #SIGUSR2
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adr x1, tickle_handler
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mov w2, #SA_SIGINFO
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orr w2, w2, #SA_NODEFER
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bl setsignal
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#ifdef SSVE
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puts "Streaming mode "
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smstart_sm
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#endif
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// Sanity-check and report the vector length
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rdvl x19, #8
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cmp x19, #128
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b.lo 1f
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cmp x19, #2048
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b.hi 1f
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tst x19, #(8 - 1)
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b.eq 2f
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1: puts "Bad vector length: "
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mov x0, x19
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bl putdecn
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b .Labort
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2: puts "Vector length:\t"
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mov x0, x19
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bl putdec
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puts " bits\n"
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// Obtain our PID, to ensure test pattern uniqueness between processes
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mov x8, #__NR_getpid
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svc #0
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mov x20, x0
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puts "PID:\t"
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mov x0, x20
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bl putdecn
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#ifdef SSVE
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smstart_sm // syscalls will have exited streaming mode
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#endif
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mov x22, #0 // generation number, increments per iteration
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.Ltest_loop:
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rdvl x0, #8
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cmp x0, x19
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b.ne vl_barf
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mov x21, #0 // Set up Z-regs & shadow with test pattern
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0: mov x0, x20
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mov x1, x21
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and x2, x22, #0xf
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bl setup_zreg
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add x21, x21, #1
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cmp x21, #NZR
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b.lo 0b
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mov x0, x20 // Set up FFR & shadow with test pattern
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mov x1, #NZR + NPR
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and x2, x22, #0xf
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bl setup_ffr
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0: mov x0, x20 // Set up P-regs & shadow with test pattern
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mov x1, x21
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and x2, x22, #0xf
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bl setup_preg
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add x21, x21, #1
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cmp x21, #NZR + NPR
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b.lo 0b
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// Can't do this when SVE state is volatile across SVC:
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// mov x8, #__NR_sched_yield // Encourage preemption
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// svc #0
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mov x21, #0
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0: mov x0, x21
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bl check_zreg
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add x21, x21, #1
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cmp x21, #NZR
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b.lo 0b
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0: mov x0, x21
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bl check_preg
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add x21, x21, #1
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cmp x21, #NZR + NPR
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b.lo 0b
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bl check_ffr
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add x22, x22, #1
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b .Ltest_loop
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.Labort:
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mov x0, #0
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mov x1, #SIGABRT
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mov x8, #__NR_kill
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svc #0
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endfunction
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function barf
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// fpsimd.c acitivty log dump hack
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// ldr w0, =0xdeadc0de
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// mov w8, #__NR_exit
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// svc #0
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// end hack
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mov x10, x0 // expected data
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mov x11, x1 // actual data
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mov x12, x2 // data size
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puts "Mismatch: PID="
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mov x0, x20
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bl putdec
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puts ", iteration="
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mov x0, x22
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bl putdec
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puts ", reg="
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mov x0, x21
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bl putdecn
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puts "\tExpected ["
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mov x0, x10
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mov x1, x12
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bl dumphex
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puts "]\n\tGot ["
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mov x0, x11
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mov x1, x12
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bl dumphex
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puts "]\n"
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mov x8, #__NR_getpid
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svc #0
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// fpsimd.c acitivty log dump hack
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// ldr w0, =0xdeadc0de
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// mov w8, #__NR_exit
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// svc #0
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// ^ end of hack
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mov x1, #SIGABRT
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mov x8, #__NR_kill
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svc #0
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// mov x8, #__NR_exit
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// mov x1, #1
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// svc #0
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endfunction
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function vl_barf
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mov x10, x0
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puts "Bad active VL: "
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mov x0, x10
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bl putdecn
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mov x8, #__NR_exit
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mov x1, #1
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svc #0
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endfunction
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