494 lines
14 KiB
C
494 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/acpi.h>
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#include <linux/adreno-smmu-priv.h>
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#include <linux/delay.h>
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#include <linux/of_device.h>
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#include <linux/qcom_scm.h>
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#include "arm-smmu.h"
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#include "arm-smmu-qcom.h"
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#define QCOM_DUMMY_VAL -1
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static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
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{
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return container_of(smmu, struct qcom_smmu, smmu);
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}
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static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
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int sync, int status)
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{
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unsigned int spin_cnt, delay;
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u32 reg;
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arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
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for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
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for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
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reg = arm_smmu_readl(smmu, page, status);
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if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
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return;
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cpu_relax();
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}
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udelay(delay);
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}
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qcom_smmu_tlb_sync_debug(smmu);
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}
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static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
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u32 reg)
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{
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struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
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/*
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* On the GPU device we want to process subsequent transactions after a
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* fault to keep the GPU from hanging
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*/
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reg |= ARM_SMMU_SCTLR_HUPCF;
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if (qsmmu->stall_enabled & BIT(idx))
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reg |= ARM_SMMU_SCTLR_CFCFG;
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arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
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}
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static void qcom_adreno_smmu_get_fault_info(const void *cookie,
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struct adreno_smmu_fault_info *info)
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{
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struct arm_smmu_domain *smmu_domain = (void *)cookie;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
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info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
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info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
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info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
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info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
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info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
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info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
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}
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static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
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{
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struct arm_smmu_domain *smmu_domain = (void *)cookie;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
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if (enabled)
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qsmmu->stall_enabled |= BIT(cfg->cbndx);
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else
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qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
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}
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static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
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{
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struct arm_smmu_domain *smmu_domain = (void *)cookie;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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u32 reg = 0;
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if (terminate)
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reg |= ARM_SMMU_RESUME_TERMINATE;
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arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
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}
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#define QCOM_ADRENO_SMMU_GPU_SID 0
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static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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int i;
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/*
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* The GPU will always use SID 0 so that is a handy way to uniquely
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* identify it and configure it for per-instance pagetables
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*/
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for (i = 0; i < fwspec->num_ids; i++) {
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u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
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if (sid == QCOM_ADRENO_SMMU_GPU_SID)
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return true;
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}
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return false;
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}
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static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
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const void *cookie)
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{
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struct arm_smmu_domain *smmu_domain = (void *)cookie;
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struct io_pgtable *pgtable =
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io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
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return &pgtable->cfg;
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}
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/*
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* Local implementation to configure TTBR0 with the specified pagetable config.
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* The GPU driver will call this to enable TTBR0 when per-instance pagetables
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* are active
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*/
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static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
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const struct io_pgtable_cfg *pgtbl_cfg)
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{
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struct arm_smmu_domain *smmu_domain = (void *)cookie;
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struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
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/* The domain must have split pagetables already enabled */
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if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
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return -EINVAL;
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/* If the pagetable config is NULL, disable TTBR0 */
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if (!pgtbl_cfg) {
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/* Do nothing if it is already disabled */
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if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
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return -EINVAL;
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/* Set TCR to the original configuration */
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cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
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cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
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} else {
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u32 tcr = cb->tcr[0];
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/* Don't call this again if TTBR0 is already enabled */
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if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
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return -EINVAL;
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tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
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tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
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cb->tcr[0] = tcr;
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cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
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cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
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}
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arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
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return 0;
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}
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static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_device *smmu,
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struct device *dev, int start)
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{
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int count;
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/*
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* Assign context bank 0 to the GPU device so the GPU hardware can
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* switch pagetables
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*/
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if (qcom_adreno_smmu_is_gpu_device(dev)) {
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start = 0;
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count = 1;
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} else {
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start = 1;
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count = smmu->num_context_banks;
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}
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return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
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}
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static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
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{
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const struct device_node *np = smmu->dev->of_node;
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if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
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return false;
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return true;
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}
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static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
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struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
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{
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struct adreno_smmu_priv *priv;
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smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
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/* Only enable split pagetables for the GPU device (SID 0) */
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if (!qcom_adreno_smmu_is_gpu_device(dev))
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return 0;
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/*
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* All targets that use the qcom,adreno-smmu compatible string *should*
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* be AARCH64 stage 1 but double check because the arm-smmu code assumes
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* that is the case when the TTBR1 quirk is enabled
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*/
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if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
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(smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
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(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
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pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
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/*
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* Initialize private interface with GPU:
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*/
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priv = dev_get_drvdata(dev);
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priv->cookie = smmu_domain;
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priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
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priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
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priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
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priv->set_stall = qcom_adreno_smmu_set_stall;
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priv->resume_translation = qcom_adreno_smmu_resume_translation;
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return 0;
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}
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static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
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{ .compatible = "qcom,adreno" },
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{ .compatible = "qcom,adreno-gmu" },
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{ .compatible = "qcom,mdp4" },
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{ .compatible = "qcom,mdss" },
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{ .compatible = "qcom,sc7180-mdss" },
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{ .compatible = "qcom,sc7180-mss-pil" },
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{ .compatible = "qcom,sc7280-mdss" },
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{ .compatible = "qcom,sc7280-mss-pil" },
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{ .compatible = "qcom,sc8180x-mdss" },
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{ .compatible = "qcom,sm8250-mdss" },
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{ .compatible = "qcom,sdm845-mdss" },
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{ .compatible = "qcom,sdm845-mss-pil" },
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{ }
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};
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static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
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struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
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{
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smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
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return 0;
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}
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static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
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{
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struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
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unsigned int last_s2cr;
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u32 reg;
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u32 smr;
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int i;
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/*
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* Some platforms support more than the Arm SMMU architected maximum of
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* 128 stream matching groups. For unknown reasons, the additional
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* groups don't exhibit the same behavior as the architected registers,
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* so limit the groups to 128 until the behavior is fixed for the other
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* groups.
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*/
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if (smmu->num_mapping_groups > 128) {
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dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
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smmu->num_mapping_groups = 128;
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}
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last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
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/*
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* With some firmware versions writes to S2CR of type FAULT are
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* ignored, and writing BYPASS will end up written as FAULT in the
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* register. Perform a write to S2CR to detect if this is the case and
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* if so reserve a context bank to emulate bypass streams.
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*/
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reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
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FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
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FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
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arm_smmu_gr0_write(smmu, last_s2cr, reg);
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reg = arm_smmu_gr0_read(smmu, last_s2cr);
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if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
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qsmmu->bypass_quirk = true;
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qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
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set_bit(qsmmu->bypass_cbndx, smmu->context_map);
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arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
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reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
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arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
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}
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for (i = 0; i < smmu->num_mapping_groups; i++) {
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smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
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if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
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/* Ignore valid bit for SMR mask extraction. */
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smr &= ~ARM_SMMU_SMR_VALID;
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smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
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smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
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smmu->smrs[i].valid = true;
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smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
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smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
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smmu->s2crs[i].cbndx = 0xff;
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}
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}
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return 0;
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}
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static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
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{
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struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
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struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
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u32 cbndx = s2cr->cbndx;
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u32 type = s2cr->type;
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u32 reg;
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if (qsmmu->bypass_quirk) {
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if (type == S2CR_TYPE_BYPASS) {
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/*
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* Firmware with quirky S2CR handling will substitute
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* BYPASS writes with FAULT, so point the stream to the
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* reserved context bank and ask for translation on the
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* stream
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*/
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type = S2CR_TYPE_TRANS;
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cbndx = qsmmu->bypass_cbndx;
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} else if (type == S2CR_TYPE_FAULT) {
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/*
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* Firmware with quirky S2CR handling will ignore FAULT
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* writes, so trick it to write FAULT by asking for a
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* BYPASS.
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*/
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type = S2CR_TYPE_BYPASS;
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cbndx = 0xff;
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}
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}
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reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
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FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
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FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
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arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
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}
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static int qcom_smmu_def_domain_type(struct device *dev)
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{
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const struct of_device_id *match =
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of_match_device(qcom_smmu_client_of_match, dev);
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return match ? IOMMU_DOMAIN_IDENTITY : 0;
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}
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static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
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{
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int ret;
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/*
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* To address performance degradation in non-real time clients,
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* such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
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* such as MTP and db845, whose firmwares implement secure monitor
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* call handlers to turn on/off the wait-for-safe logic.
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*/
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ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
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if (ret)
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dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
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return ret;
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}
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static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
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{
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const struct device_node *np = smmu->dev->of_node;
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arm_mmu500_reset(smmu);
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if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
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return qcom_sdm845_smmu500_reset(smmu);
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return 0;
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}
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static const struct arm_smmu_impl qcom_smmu_impl = {
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.init_context = qcom_smmu_init_context,
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.cfg_probe = qcom_smmu_cfg_probe,
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.def_domain_type = qcom_smmu_def_domain_type,
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.reset = qcom_smmu500_reset,
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.write_s2cr = qcom_smmu_write_s2cr,
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.tlb_sync = qcom_smmu_tlb_sync,
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};
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static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
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.init_context = qcom_adreno_smmu_init_context,
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.def_domain_type = qcom_smmu_def_domain_type,
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.reset = qcom_smmu500_reset,
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.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
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.write_sctlr = qcom_adreno_smmu_write_sctlr,
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.tlb_sync = qcom_smmu_tlb_sync,
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};
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static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
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const struct arm_smmu_impl *impl)
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{
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struct qcom_smmu *qsmmu;
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/* Check to make sure qcom_scm has finished probing */
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if (!qcom_scm_is_available())
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return ERR_PTR(-EPROBE_DEFER);
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qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
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if (!qsmmu)
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return ERR_PTR(-ENOMEM);
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qsmmu->smmu.impl = impl;
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qsmmu->cfg = qcom_smmu_impl_data(smmu);
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return &qsmmu->smmu;
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}
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static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
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{ .compatible = "qcom,msm8998-smmu-v2" },
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{ .compatible = "qcom,qcm2290-smmu-500" },
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{ .compatible = "qcom,sc7180-smmu-500" },
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{ .compatible = "qcom,sc7280-smmu-500" },
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{ .compatible = "qcom,sc8180x-smmu-500" },
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{ .compatible = "qcom,sc8280xp-smmu-500" },
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{ .compatible = "qcom,sdm630-smmu-v2" },
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{ .compatible = "qcom,sdm845-smmu-500" },
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{ .compatible = "qcom,sm6125-smmu-500" },
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{ .compatible = "qcom,sm6350-smmu-500" },
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{ .compatible = "qcom,sm6375-smmu-500" },
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{ .compatible = "qcom,sm8150-smmu-500" },
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{ .compatible = "qcom,sm8250-smmu-500" },
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{ .compatible = "qcom,sm8350-smmu-500" },
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{ .compatible = "qcom,sm8450-smmu-500" },
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{ }
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};
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#ifdef CONFIG_ACPI
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static struct acpi_platform_list qcom_acpi_platlist[] = {
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{ "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
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{ "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
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{ }
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};
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#endif
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struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
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{
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const struct device_node *np = smmu->dev->of_node;
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#ifdef CONFIG_ACPI
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if (np == NULL) {
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/* Match platform for ACPI boot */
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if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
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return qcom_smmu_create(smmu, &qcom_smmu_impl);
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}
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#endif
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/*
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* Do not change this order of implementation, i.e., first adreno
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* smmu impl and then apss smmu since we can have both implementing
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* arm,mmu-500 in which case we will miss setting adreno smmu specific
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* features if the order is changed.
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*/
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if (of_device_is_compatible(np, "qcom,adreno-smmu"))
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return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
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if (of_match_node(qcom_smmu_impl_of_match, np))
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return qcom_smmu_create(smmu, &qcom_smmu_impl);
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return smmu;
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}
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