215 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
			
		
		
	
	
			215 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: panel timing bindings
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maintainers:
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  - Thierry Reding <thierry.reding@gmail.com>
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  - Sam Ravnborg <sam@ravnborg.org>
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description: |
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  There are different ways of describing the timing data of a panel. The
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  devicetree representation corresponds to the one commonly found in datasheets
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  for panels.
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  The parameters are defined as seen in the following illustration.
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  +----------+-------------------------------------+----------+-------+
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  |          |        ^                            |          |       |
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  |          |        |vback_porch                 |          |       |
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  |          |        v                            |          |       |
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  +----------#######################################----------+-------+
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  |          #        ^                            #          |       |
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  |          #        |                            #          |       |
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  |  hback   #        |                            #  hfront  | hsync |
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  |   porch  #        |       hactive              #  porch   |  len  |
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  |<-------->#<-------+--------------------------->#<-------->|<----->|
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  |          #        |                            #          |       |
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  |          #        |vactive                     #          |       |
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  |          #        |                            #          |       |
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  |          #        v                            #          |       |
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  +----------#######################################----------+-------+
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  |          |        ^                            |          |       |
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  |          |        |vfront_porch                |          |       |
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  |          |        v                            |          |       |
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  +----------+-------------------------------------+----------+-------+
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  |          |        ^                            |          |       |
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  |          |        |vsync_len                   |          |       |
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  |          |        v                            |          |       |
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  +----------+-------------------------------------+----------+-------+
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  The following is the panel timings shown with time on the x-axis.
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  This matches the timing diagrams often found in data sheets.
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              Active                 Front           Sync           Back
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              Region                 Porch                          Porch
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  <-----------------------><----------------><-------------><-------------->
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    //////////////////////|
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   ////////////////////// |
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  //////////////////////  |..................               ................
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                                             _______________
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  Timing can be specified either as a typical value or as a tuple
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  of min, typ, max values.
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properties:
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  clock-frequency:
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    description: Panel clock in Hz
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  hactive:
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    $ref: /schemas/types.yaml#/definitions/uint32
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    description: Horizontal panel resolution in pixels
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  vactive:
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    $ref: /schemas/types.yaml#/definitions/uint32
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    description: Vertical panel resolution in pixels
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  hfront-porch:
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    description: Horizontal front porch panel timing
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    $ref: /schemas/types.yaml#/definitions/uint32-array
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    oneOf:
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      - maxItems: 1
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        items:
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          description: typical number of pixels
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      - minItems: 3
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        maxItems: 3
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        items:
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          description: min, typ, max number of pixels
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  hback-porch:
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    description: Horizontal back porch timing
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    $ref: /schemas/types.yaml#/definitions/uint32-array
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    oneOf:
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      - maxItems: 1
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        items:
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          description: typical number of pixels
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      - minItems: 3
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        maxItems: 3
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        items:
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          description: min, typ, max number of pixels
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  hsync-len:
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    description: Horizontal sync length panel timing
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    $ref: /schemas/types.yaml#/definitions/uint32-array
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    oneOf:
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      - maxItems: 1
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        items:
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          description: typical number of pixels
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      - minItems: 3
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        maxItems: 3
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        items:
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          description: min, typ, max number of pixels
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  vfront-porch:
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    description: Vertical front porch panel timing
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    $ref: /schemas/types.yaml#/definitions/uint32-array
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    oneOf:
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      - maxItems: 1
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        items:
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          description: typical number of lines
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      - minItems: 3
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        maxItems: 3
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        items:
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          description: min, typ, max number of lines
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  vback-porch:
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    description: Vertical back porch panel timing
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    $ref: /schemas/types.yaml#/definitions/uint32-array
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    oneOf:
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      - maxItems: 1
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        items:
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          description: typical number of lines
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      - minItems: 3
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        maxItems: 3
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        items:
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          description: min, typ, max number of lines
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  vsync-len:
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    description: Vertical sync length panel timing
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    $ref: /schemas/types.yaml#/definitions/uint32-array
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    oneOf:
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      - maxItems: 1
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        items:
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          description: typical number of lines
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      - minItems: 3
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        maxItems: 3
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        items:
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          description: min, typ, max number of lines
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  hsync-active:
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    description: |
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      Horizontal sync pulse.
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      0 selects active low, 1 selects active high.
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      If omitted then it is not used by the hardware
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    $ref: /schemas/types.yaml#/definitions/uint32
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    enum: [0, 1]
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  vsync-active:
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    description: |
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      Vertical sync pulse.
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      0 selects active low, 1 selects active high.
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      If omitted then it is not used by the hardware
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    $ref: /schemas/types.yaml#/definitions/uint32
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    enum: [0, 1]
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  de-active:
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    description: |
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      Data enable.
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      0 selects active low, 1 selects active high.
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      If omitted then it is not used by the hardware
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    $ref: /schemas/types.yaml#/definitions/uint32
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    enum: [0, 1]
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  pixelclk-active:
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    description: |
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      Data driving on rising or falling edge.
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      Use 0 to drive pixel data on falling edge and
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      sample data on rising edge.
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      Use 1 to drive pixel data on rising edge and
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      sample data on falling edge
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    $ref: /schemas/types.yaml#/definitions/uint32
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    enum: [0, 1]
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  syncclk-active:
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    description: |
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      Drive sync on rising or sample sync on falling edge.
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      If not specified then the setup is as specified by pixelclk-active.
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      Use 0 to drive sync on falling edge and
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      sample sync on rising edge of pixel clock.
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      Use 1 to drive sync on rising edge and
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      sample sync on falling edge of pixel clock
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    $ref: /schemas/types.yaml#/definitions/uint32
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    enum: [0, 1]
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  interlaced:
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    type: boolean
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    description: Enable interlaced mode
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  doublescan:
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    type: boolean
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    description: Enable double scan mode
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  doubleclk:
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    type: boolean
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    description: Enable double clock mode
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required:
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  - clock-frequency
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  - hactive
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  - vactive
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  - hfront-porch
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  - hback-porch
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  - hsync-len
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  - vfront-porch
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  - vback-porch
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  - vsync-len
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additionalProperties: false
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...
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