358 lines
12 KiB
C
Executable File
358 lines
12 KiB
C
Executable File
/*
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* Copyright (C) 2011-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "mali_gp.h"
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#include "mali_hw_core.h"
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#include "mali_group.h"
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#include "mali_osk.h"
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#include "regs/mali_gp_regs.h"
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#include "mali_kernel_common.h"
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#include "mali_kernel_core.h"
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#if defined(CONFIG_MALI400_PROFILING)
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#include "mali_osk_profiling.h"
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#endif
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static struct mali_gp_core *mali_global_gp_core = NULL;
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/* Interrupt handlers */
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static void mali_gp_irq_probe_trigger(void *data);
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static _mali_osk_errcode_t mali_gp_irq_probe_ack(void *data);
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struct mali_gp_core *mali_gp_create(const _mali_osk_resource_t *resource, struct mali_group *group)
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{
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struct mali_gp_core *core = NULL;
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MALI_DEBUG_ASSERT(NULL == mali_global_gp_core);
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MALI_DEBUG_PRINT(2, ("Mali GP: Creating Mali GP core: %s\n", resource->description));
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core = _mali_osk_malloc(sizeof(struct mali_gp_core));
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if (NULL != core) {
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if (_MALI_OSK_ERR_OK == mali_hw_core_create(&core->hw_core, resource, MALIGP2_REGISTER_ADDRESS_SPACE_SIZE)) {
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_mali_osk_errcode_t ret;
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ret = mali_gp_reset(core);
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if (_MALI_OSK_ERR_OK == ret) {
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ret = mali_group_add_gp_core(group, core);
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if (_MALI_OSK_ERR_OK == ret) {
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/* Setup IRQ handlers (which will do IRQ probing if needed) */
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core->irq = _mali_osk_irq_init(resource->irq,
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mali_group_upper_half_gp,
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group,
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mali_gp_irq_probe_trigger,
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mali_gp_irq_probe_ack,
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core,
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resource->description);
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if (NULL != core->irq) {
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MALI_DEBUG_PRINT(4, ("Mali GP: set global gp core from 0x%08X to 0x%08X\n", mali_global_gp_core, core));
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mali_global_gp_core = core;
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return core;
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} else {
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MALI_PRINT_ERROR(("Mali GP: Failed to setup interrupt handlers for GP core %s\n", core->hw_core.description));
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}
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mali_group_remove_gp_core(group);
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} else {
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MALI_PRINT_ERROR(("Mali GP: Failed to add core %s to group\n", core->hw_core.description));
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}
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}
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mali_hw_core_delete(&core->hw_core);
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}
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_mali_osk_free(core);
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} else {
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MALI_PRINT_ERROR(("Failed to allocate memory for GP core\n"));
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}
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return NULL;
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}
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void mali_gp_delete(struct mali_gp_core *core)
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{
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MALI_DEBUG_ASSERT_POINTER(core);
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_mali_osk_irq_term(core->irq);
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mali_hw_core_delete(&core->hw_core);
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mali_global_gp_core = NULL;
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_mali_osk_free(core);
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}
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void mali_gp_stop_bus(struct mali_gp_core *core)
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{
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MALI_DEBUG_ASSERT_POINTER(core);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_STOP_BUS);
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}
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_mali_osk_errcode_t mali_gp_stop_bus_wait(struct mali_gp_core *core)
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{
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int i;
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MALI_DEBUG_ASSERT_POINTER(core);
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/* Send the stop bus command. */
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mali_gp_stop_bus(core);
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/* Wait for bus to be stopped */
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for (i = 0; i < MALI_REG_POLL_COUNT_SLOW; i++) {
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if (mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS) & MALIGP2_REG_VAL_STATUS_BUS_STOPPED) {
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break;
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}
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}
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if (MALI_REG_POLL_COUNT_SLOW == i) {
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MALI_PRINT_ERROR(("Mali GP: Failed to stop bus on %s\n", core->hw_core.description));
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return _MALI_OSK_ERR_FAULT;
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}
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return _MALI_OSK_ERR_OK;
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}
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void mali_gp_hard_reset(struct mali_gp_core *core)
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{
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const u32 reset_wait_target_register = MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_LIMIT;
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const u32 reset_invalid_value = 0xC0FFE000;
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const u32 reset_check_value = 0xC01A0000;
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const u32 reset_default_value = 0;
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int i;
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MALI_DEBUG_ASSERT_POINTER(core);
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MALI_DEBUG_PRINT(4, ("Mali GP: Hard reset of core %s\n", core->hw_core.description));
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mali_hw_core_register_write(&core->hw_core, reset_wait_target_register, reset_invalid_value);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_RESET);
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for (i = 0; i < MALI_REG_POLL_COUNT_FAST; i++) {
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mali_hw_core_register_write(&core->hw_core, reset_wait_target_register, reset_check_value);
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if (reset_check_value == mali_hw_core_register_read(&core->hw_core, reset_wait_target_register)) {
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break;
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}
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}
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if (MALI_REG_POLL_COUNT_FAST == i) {
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MALI_PRINT_ERROR(("Mali GP: The hard reset loop didn't work, unable to recover\n"));
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}
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mali_hw_core_register_write(&core->hw_core, reset_wait_target_register, reset_default_value); /* set it back to the default */
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/* Re-enable interrupts */
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_MASK_ALL);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED);
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}
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void mali_gp_reset_async(struct mali_gp_core *core)
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{
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MALI_DEBUG_ASSERT_POINTER(core);
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MALI_DEBUG_PRINT(4, ("Mali GP: Reset of core %s\n", core->hw_core.description));
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, 0); /* disable the IRQs */
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALI400GP_REG_VAL_IRQ_RESET_COMPLETED);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALI400GP_REG_VAL_CMD_SOFT_RESET);
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}
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_mali_osk_errcode_t mali_gp_reset_wait(struct mali_gp_core *core)
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{
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int i;
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u32 rawstat = 0;
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MALI_DEBUG_ASSERT_POINTER(core);
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for (i = 0; i < MALI_REG_POLL_COUNT_FAST; i++) {
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rawstat = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT);
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if (rawstat & MALI400GP_REG_VAL_IRQ_RESET_COMPLETED) {
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break;
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}
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}
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if (i == MALI_REG_POLL_COUNT_FAST) {
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MALI_PRINT_ERROR(("Mali GP: Failed to reset core %s, rawstat: 0x%08x\n",
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core->hw_core.description, rawstat));
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return _MALI_OSK_ERR_FAULT;
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}
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/* Re-enable interrupts */
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_MASK_ALL);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED);
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return _MALI_OSK_ERR_OK;
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}
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_mali_osk_errcode_t mali_gp_reset(struct mali_gp_core *core)
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{
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mali_gp_reset_async(core);
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return mali_gp_reset_wait(core);
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}
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void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
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{
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u32 startcmd = 0;
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u32 *frame_registers = mali_gp_job_get_frame_registers(job);
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u32 counter_src0 = mali_gp_job_get_perf_counter_src0(job);
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u32 counter_src1 = mali_gp_job_get_perf_counter_src1(job);
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MALI_DEBUG_ASSERT_POINTER(core);
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if (mali_gp_job_has_vs_job(job)) {
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startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
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}
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if (mali_gp_job_has_plbu_job(job)) {
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startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
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}
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MALI_DEBUG_ASSERT(0 != startcmd);
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mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
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if (MALI_HW_CORE_NO_COUNTER != counter_src0) {
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, counter_src0);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
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}
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if (MALI_HW_CORE_NO_COUNTER != counter_src1) {
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, counter_src1);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
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}
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MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
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mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC);
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/* Barrier to make sure the previous register write is finished */
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_mali_osk_write_mem_barrier();
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/* This is the command that starts the core.
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*
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* Don't actually run the job if PROFILING_SKIP_PP_JOBS are set, just
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* force core to assert the completion interrupt.
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*/
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#if !defined(PROFILING_SKIP_GP_JOBS)
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mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
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#else
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{
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u32 bits = 0;
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if (mali_gp_job_has_vs_job(job))
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bits = MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST;
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if (mali_gp_job_has_plbu_job(job))
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bits |= MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST;
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mali_hw_core_register_write_relaxed(&core->hw_core,
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MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT, bits);
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}
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#endif
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/* Barrier to make sure the previous register write is finished */
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_mali_osk_write_mem_barrier();
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}
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void mali_gp_resume_with_new_heap(struct mali_gp_core *core, u32 start_addr, u32 end_addr)
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{
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u32 irq_readout;
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MALI_DEBUG_ASSERT_POINTER(core);
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irq_readout = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT);
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if (irq_readout & MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM) {
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, (MALIGP2_REG_VAL_IRQ_PLBU_OUT_OF_MEM | MALIGP2_REG_VAL_IRQ_HANG));
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED); /* re-enable interrupts */
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mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR, start_addr);
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mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_END_ADDR, end_addr);
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MALI_DEBUG_PRINT(3, ("Mali GP: Resuming job\n"));
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC);
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_mali_osk_write_mem_barrier();
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}
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/*
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* else: core has been reset between PLBU_OUT_OF_MEM interrupt and this new heap response.
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* A timeout or a page fault on Mali-200 PP core can cause this behaviour.
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*/
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}
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u32 mali_gp_core_get_version(struct mali_gp_core *core)
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{
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MALI_DEBUG_ASSERT_POINTER(core);
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return mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VERSION);
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}
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struct mali_gp_core *mali_gp_get_global_gp_core(void)
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{
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return mali_global_gp_core;
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}
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/* ------------- interrupt handling below ------------------ */
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static void mali_gp_irq_probe_trigger(void *data)
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{
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struct mali_gp_core *core = (struct mali_gp_core *)data;
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED);
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT, MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR);
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_mali_osk_mem_barrier();
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}
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static _mali_osk_errcode_t mali_gp_irq_probe_ack(void *data)
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{
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struct mali_gp_core *core = (struct mali_gp_core *)data;
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u32 irq_readout;
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irq_readout = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_STAT);
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if (MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR & irq_readout) {
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mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_CLEAR, MALIGP2_REG_VAL_IRQ_AXI_BUS_ERROR);
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_mali_osk_mem_barrier();
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return _MALI_OSK_ERR_OK;
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}
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return _MALI_OSK_ERR_FAULT;
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}
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/* ------ local helper functions below --------- */
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#if MALI_STATE_TRACKING
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u32 mali_gp_dump_state(struct mali_gp_core *core, char *buf, u32 size)
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{
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int n = 0;
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n += _mali_osk_snprintf(buf + n, size - n, "\tGP: %s\n", core->hw_core.description);
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return n;
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}
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#endif
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void mali_gp_update_performance_counters(struct mali_gp_core *core, struct mali_gp_job *job)
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{
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u32 val0 = 0;
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u32 val1 = 0;
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u32 counter_src0 = mali_gp_job_get_perf_counter_src0(job);
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u32 counter_src1 = mali_gp_job_get_perf_counter_src1(job);
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if (MALI_HW_CORE_NO_COUNTER != counter_src0) {
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val0 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
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mali_gp_job_set_perf_counter_value0(job, val0);
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#if defined(CONFIG_MALI400_PROFILING)
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_mali_osk_profiling_report_hw_counter(COUNTER_VP_0_C0, val0);
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_mali_osk_profiling_record_global_counters(COUNTER_VP_0_C0, val0);
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#endif
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}
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if (MALI_HW_CORE_NO_COUNTER != counter_src1) {
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val1 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
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mali_gp_job_set_perf_counter_value1(job, val1);
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#if defined(CONFIG_MALI400_PROFILING)
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_mali_osk_profiling_report_hw_counter(COUNTER_VP_0_C1, val1);
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_mali_osk_profiling_record_global_counters(COUNTER_VP_0_C1, val1);
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#endif
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}
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}
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