156 lines
2.7 KiB
JSON
156 lines
2.7 KiB
JSON
[
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L1D_TLB"
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},
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{
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"ArchStdEvent": "L1I_TLB"
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},
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{
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"ArchStdEvent": "L3D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L3D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L3D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2D_TLB"
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},
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{
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"ArchStdEvent": "DTLB_WALK"
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},
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{
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"ArchStdEvent": "ITLB_WALK"
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},
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{
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"ArchStdEvent": "LL_CACHE_RD"
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},
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{
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"ArchStdEvent": "LL_CACHE_MISS_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_LMISS_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L1D_TLB_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_TLB_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_WR"
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},
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{
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"ArchStdEvent": "L3D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1I_CACHE_LMISS"
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},
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{
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"ArchStdEvent": "L2D_CACHE_LMISS_RD"
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},
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{
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"ArchStdEvent": "L3D_CACHE_LMISS_RD"
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}
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]
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