652 lines
17 KiB
C
652 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Xtfpga I2S controller driver
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*
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* Copyright (c) 2014 Cadence Design Systems Inc.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#define DRV_NAME "xtfpga-i2s"
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#define XTFPGA_I2S_VERSION 0x00
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#define XTFPGA_I2S_CONFIG 0x04
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#define XTFPGA_I2S_INT_MASK 0x08
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#define XTFPGA_I2S_INT_STATUS 0x0c
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#define XTFPGA_I2S_CHAN0_DATA 0x10
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#define XTFPGA_I2S_CHAN1_DATA 0x14
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#define XTFPGA_I2S_CHAN2_DATA 0x18
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#define XTFPGA_I2S_CHAN3_DATA 0x1c
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#define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
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#define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
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#define XTFPGA_I2S_CONFIG_LEFT 0x4
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#define XTFPGA_I2S_CONFIG_RATIO_BASE 8
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#define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
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#define XTFPGA_I2S_CONFIG_RES_BASE 16
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#define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
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#define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
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#define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
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#define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
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#define XTFPGA_I2S_INT_UNDERRUN 0x1
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#define XTFPGA_I2S_INT_LEVEL 0x2
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#define XTFPGA_I2S_INT_VALID 0x3
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#define XTFPGA_I2S_FIFO_SIZE 8192
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/*
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* I2S controller operation:
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*
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* Enabling TX: output 1 period of zeros (starting with left channel)
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* and then queued data.
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*
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* Level status and interrupt: whenever FIFO level is below FIFO trigger,
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* level status is 1 and an IRQ is asserted (if enabled).
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*
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* Underrun status and interrupt: whenever FIFO is empty, underrun status
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* is 1 and an IRQ is asserted (if enabled).
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*/
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struct xtfpga_i2s {
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struct device *dev;
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struct clk *clk;
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struct regmap *regmap;
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void __iomem *regs;
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/* current playback substream. NULL if not playing.
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*
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* Access to that field is synchronized between the interrupt handler
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* and userspace through RCU.
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*
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* Interrupt handler (threaded part) does PIO on substream data in RCU
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* read-side critical section. Trigger callback sets and clears the
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* pointer when the playback is started and stopped with
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* rcu_assign_pointer. When userspace is about to free the playback
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* stream in the pcm_close callback it synchronizes with the interrupt
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* handler by means of synchronize_rcu call.
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*/
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struct snd_pcm_substream __rcu *tx_substream;
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unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
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struct snd_pcm_runtime *runtime,
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unsigned tx_ptr);
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unsigned tx_ptr; /* next frame index in the sample buffer */
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/* current fifo level estimate.
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* Doesn't have to be perfectly accurate, but must be not less than
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* the actual FIFO level in order to avoid stall on push attempt.
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*/
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unsigned tx_fifo_level;
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/* FIFO level at which level interrupt occurs */
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unsigned tx_fifo_low;
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/* maximal FIFO level */
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unsigned tx_fifo_high;
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};
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static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
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{
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return reg >= XTFPGA_I2S_CONFIG;
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}
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static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
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{
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return reg < XTFPGA_I2S_CHAN0_DATA;
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}
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static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
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{
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return reg == XTFPGA_I2S_INT_STATUS;
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}
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static const struct regmap_config xtfpga_i2s_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = XTFPGA_I2S_CHAN3_DATA,
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.writeable_reg = xtfpga_i2s_wr_reg,
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.readable_reg = xtfpga_i2s_rd_reg,
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.volatile_reg = xtfpga_i2s_volatile_reg,
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.cache_type = REGCACHE_FLAT,
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};
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/* Generate functions that do PIO from TX DMA area to FIFO for all supported
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* stream formats.
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* Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
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* xtfpga_pcm_tx_2x16 for 16-bit stereo.
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*
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* FIFO consists of 32-bit words, one word per channel, always 2 channels.
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* If I2S interface is configured with smaller sample resolution, only
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* the LSB of each word is used.
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*/
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#define xtfpga_pcm_tx_fn(channels, sample_bits) \
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static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
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struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
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unsigned tx_ptr) \
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{ \
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const u##sample_bits (*p)[channels] = \
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(void *)runtime->dma_area; \
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\
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for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
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i2s->tx_fifo_level += 2) { \
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iowrite32(p[tx_ptr][0], \
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i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
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iowrite32(p[tx_ptr][channels - 1], \
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i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
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if (++tx_ptr >= runtime->buffer_size) \
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tx_ptr = 0; \
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} \
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return tx_ptr; \
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}
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xtfpga_pcm_tx_fn(1, 16)
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xtfpga_pcm_tx_fn(2, 16)
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xtfpga_pcm_tx_fn(1, 32)
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xtfpga_pcm_tx_fn(2, 32)
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#undef xtfpga_pcm_tx_fn
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static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
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{
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struct snd_pcm_substream *tx_substream;
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bool tx_active;
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rcu_read_lock();
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tx_substream = rcu_dereference(i2s->tx_substream);
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tx_active = tx_substream && snd_pcm_running(tx_substream);
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if (tx_active) {
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unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
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unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
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tx_ptr);
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cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
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}
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rcu_read_unlock();
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return tx_active;
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}
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static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
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{
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unsigned int_status;
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unsigned i;
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regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
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&int_status);
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for (i = 0; i < 2; ++i) {
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bool tx_active = xtfpga_pcm_push_tx(i2s);
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regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
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XTFPGA_I2S_INT_VALID);
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if (tx_active)
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regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
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&int_status);
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if (!tx_active ||
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!(int_status & XTFPGA_I2S_INT_LEVEL))
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break;
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/* After the push the level IRQ is still asserted,
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* means FIFO level is below tx_fifo_low. Estimate
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* it as tx_fifo_low.
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*/
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i2s->tx_fifo_level = i2s->tx_fifo_low;
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}
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if (!(int_status & XTFPGA_I2S_INT_LEVEL))
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regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
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XTFPGA_I2S_INT_VALID);
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else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
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regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
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XTFPGA_I2S_INT_UNDERRUN);
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if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
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regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
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XTFPGA_I2S_CONFIG_INT_ENABLE |
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XTFPGA_I2S_CONFIG_TX_ENABLE,
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XTFPGA_I2S_CONFIG_INT_ENABLE |
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XTFPGA_I2S_CONFIG_TX_ENABLE);
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else
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regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
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XTFPGA_I2S_CONFIG_INT_ENABLE |
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XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
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}
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static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
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{
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struct xtfpga_i2s *i2s = dev_id;
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struct snd_pcm_substream *tx_substream;
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unsigned config, int_status, int_mask;
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regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
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regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
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regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
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if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
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!(int_status & int_mask & XTFPGA_I2S_INT_VALID))
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return IRQ_NONE;
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/* Update FIFO level estimate in accordance with interrupt status
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* register.
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*/
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if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
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i2s->tx_fifo_level = 0;
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regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
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XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
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} else {
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/* The FIFO isn't empty, but is below tx_fifo_low. Estimate
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* it as tx_fifo_low.
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*/
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i2s->tx_fifo_level = i2s->tx_fifo_low;
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}
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rcu_read_lock();
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tx_substream = rcu_dereference(i2s->tx_substream);
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if (tx_substream && snd_pcm_running(tx_substream)) {
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snd_pcm_period_elapsed(tx_substream);
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if (int_status & XTFPGA_I2S_INT_UNDERRUN)
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dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
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__func__);
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}
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rcu_read_unlock();
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/* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
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* not empty.
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*/
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xtfpga_pcm_refill_fifo(i2s);
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return IRQ_HANDLED;
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}
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static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_set_dma_data(dai, substream, i2s);
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return 0;
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}
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static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned srate = params_rate(params);
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unsigned channels = params_channels(params);
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unsigned period_size = params_period_size(params);
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unsigned sample_size = snd_pcm_format_width(params_format(params));
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unsigned freq, ratio, level;
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int err;
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regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
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XTFPGA_I2S_CONFIG_RES_MASK,
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sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
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freq = 256 * srate;
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err = clk_set_rate(i2s->clk, freq);
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if (err < 0)
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return err;
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/* ratio field of the config register controls MCLK->I2S clock
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* derivation: I2S clock = MCLK / (2 * (ratio + 2)).
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*
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* So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
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* and 2 for 16 bit stereo.
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*/
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ratio = (freq - (srate * sample_size * 8)) /
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(srate * sample_size * 4);
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regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
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XTFPGA_I2S_CONFIG_RATIO_MASK,
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ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
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i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
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/* period_size * 2: FIFO always gets 2 samples per frame */
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for (level = 1;
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i2s->tx_fifo_low / 2 >= period_size * 2 &&
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level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
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XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
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i2s->tx_fifo_low /= 2;
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i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
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regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
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XTFPGA_I2S_CONFIG_LEVEL_MASK,
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level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
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dev_dbg(i2s->dev,
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"%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
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__func__, srate, channels, sample_size, period_size);
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dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
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__func__, freq, ratio, level);
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return 0;
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}
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static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
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return -EINVAL;
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if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP)
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return -EINVAL;
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if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
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return -EINVAL;
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return 0;
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}
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/* PCM */
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static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_BLOCK_TRANSFER,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 1,
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.channels_max = 2,
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.period_bytes_min = 2,
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.period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
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.periods_min = 2,
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.periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
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.buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
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.fifo_size = 16,
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};
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static int xtfpga_pcm_open(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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void *p;
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snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
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p = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
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runtime->private_data = p;
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return 0;
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}
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static int xtfpga_pcm_close(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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synchronize_rcu();
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return 0;
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}
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static int xtfpga_pcm_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct xtfpga_i2s *i2s = runtime->private_data;
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unsigned channels = params_channels(hw_params);
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switch (channels) {
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case 1:
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case 2:
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break;
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default:
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return -EINVAL;
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}
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switch (params_format(hw_params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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i2s->tx_fn = (channels == 1) ?
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xtfpga_pcm_tx_1x16 :
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xtfpga_pcm_tx_2x16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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i2s->tx_fn = (channels == 1) ?
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xtfpga_pcm_tx_1x32 :
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xtfpga_pcm_tx_2x32;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int xtfpga_pcm_trigger(struct snd_soc_component *component,
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struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct xtfpga_i2s *i2s = runtime->private_data;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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WRITE_ONCE(i2s->tx_ptr, 0);
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rcu_assign_pointer(i2s->tx_substream, substream);
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xtfpga_pcm_refill_fifo(i2s);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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rcu_assign_pointer(i2s->tx_substream, NULL);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
|
|
struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct xtfpga_i2s *i2s = runtime->private_data;
|
|
snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
|
|
|
|
return pos < runtime->buffer_size ? pos : 0;
|
|
}
|
|
|
|
static int xtfpga_pcm_new(struct snd_soc_component *component,
|
|
struct snd_soc_pcm_runtime *rtd)
|
|
{
|
|
struct snd_card *card = rtd->card->snd_card;
|
|
size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
|
|
|
|
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
|
|
card->dev, size, size);
|
|
return 0;
|
|
}
|
|
|
|
static const struct snd_soc_component_driver xtfpga_i2s_component = {
|
|
.name = DRV_NAME,
|
|
.open = xtfpga_pcm_open,
|
|
.close = xtfpga_pcm_close,
|
|
.hw_params = xtfpga_pcm_hw_params,
|
|
.trigger = xtfpga_pcm_trigger,
|
|
.pointer = xtfpga_pcm_pointer,
|
|
.pcm_construct = xtfpga_pcm_new,
|
|
.legacy_dai_naming = 1,
|
|
};
|
|
|
|
static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
|
|
.startup = xtfpga_i2s_startup,
|
|
.hw_params = xtfpga_i2s_hw_params,
|
|
.set_fmt = xtfpga_i2s_set_fmt,
|
|
};
|
|
|
|
static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
|
|
{
|
|
.name = "xtfpga-i2s",
|
|
.id = 0,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.ops = &xtfpga_i2s_dai_ops,
|
|
},
|
|
};
|
|
|
|
static int xtfpga_i2s_runtime_suspend(struct device *dev)
|
|
{
|
|
struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(i2s->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int xtfpga_i2s_runtime_resume(struct device *dev)
|
|
{
|
|
struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(i2s->clk);
|
|
if (ret) {
|
|
dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int xtfpga_i2s_probe(struct platform_device *pdev)
|
|
{
|
|
struct xtfpga_i2s *i2s;
|
|
int err, irq;
|
|
|
|
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
|
|
if (!i2s) {
|
|
err = -ENOMEM;
|
|
goto err;
|
|
}
|
|
platform_set_drvdata(pdev, i2s);
|
|
i2s->dev = &pdev->dev;
|
|
dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
|
|
|
|
i2s->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(i2s->regs)) {
|
|
err = PTR_ERR(i2s->regs);
|
|
goto err;
|
|
}
|
|
|
|
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
|
|
&xtfpga_i2s_regmap_config);
|
|
if (IS_ERR(i2s->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
err = PTR_ERR(i2s->regmap);
|
|
goto err;
|
|
}
|
|
|
|
i2s->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(i2s->clk)) {
|
|
dev_err(&pdev->dev, "couldn't get clock\n");
|
|
err = PTR_ERR(i2s->clk);
|
|
goto err;
|
|
}
|
|
|
|
regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
|
|
(0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
|
|
regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
|
|
regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
err = irq;
|
|
goto err;
|
|
}
|
|
err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
|
|
xtfpga_i2s_threaded_irq_handler,
|
|
IRQF_SHARED | IRQF_ONESHOT,
|
|
pdev->name, i2s);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "request_irq failed\n");
|
|
goto err;
|
|
}
|
|
|
|
err = devm_snd_soc_register_component(&pdev->dev,
|
|
&xtfpga_i2s_component,
|
|
xtfpga_i2s_dai,
|
|
ARRAY_SIZE(xtfpga_i2s_dai));
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "couldn't register component\n");
|
|
goto err;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
err = xtfpga_i2s_runtime_resume(&pdev->dev);
|
|
if (err)
|
|
goto err_pm_disable;
|
|
}
|
|
return 0;
|
|
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err:
|
|
dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
|
|
return err;
|
|
}
|
|
|
|
static int xtfpga_i2s_remove(struct platform_device *pdev)
|
|
{
|
|
struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
|
|
|
|
if (i2s->regmap && !IS_ERR(i2s->regmap)) {
|
|
regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
|
|
regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
|
|
regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
|
|
XTFPGA_I2S_INT_VALID);
|
|
}
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
xtfpga_i2s_runtime_suspend(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id xtfpga_i2s_of_match[] = {
|
|
{ .compatible = "cdns,xtfpga-i2s", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
|
|
#endif
|
|
|
|
static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
|
|
xtfpga_i2s_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver xtfpga_i2s_driver = {
|
|
.probe = xtfpga_i2s_probe,
|
|
.remove = xtfpga_i2s_remove,
|
|
.driver = {
|
|
.name = "xtfpga-i2s",
|
|
.of_match_table = of_match_ptr(xtfpga_i2s_of_match),
|
|
.pm = &xtfpga_i2s_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(xtfpga_i2s_driver);
|
|
|
|
MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
|
|
MODULE_DESCRIPTION("xtfpga I2S controller driver");
|
|
MODULE_LICENSE("GPL v2");
|