435 lines
12 KiB
C
435 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// tegra210_peq.c - Tegra210 PEQ driver
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//
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// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra210_ope.h"
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#include "tegra210_peq.h"
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static const struct reg_default tegra210_peq_reg_defaults[] = {
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{ TEGRA210_PEQ_CFG, 0x00000013},
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{ TEGRA210_PEQ_CFG_RAM_CTRL, 0x00004000},
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{ TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL, 0x00004000},
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};
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static const u32 biquad_init_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH] = {
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1495012349, /* Pre-gain */
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/* Gains : b0, b1, a0, a1, a2 */
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536870912, -1073741824, 536870912, 2143508246, -1069773768, /* Band-0 */
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134217728, -265414508, 131766272, 2140402222, -1071252997, /* Band-1 */
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268435456, -233515765, -33935948, 1839817267, -773826124, /* Band-2 */
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536870912, -672537913, 139851540, 1886437554, -824433167, /* Band-3 */
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268435456, -114439279, 173723964, 205743566, 278809729, /* Band-4 */
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1, 0, 0, 0, 0, /* Band-5 */
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1, 0, 0, 0, 0, /* Band-6 */
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1, 0, 0, 0, 0, /* Band-7 */
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1, 0, 0, 0, 0, /* Band-8 */
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1, 0, 0, 0, 0, /* Band-9 */
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1, 0, 0, 0, 0, /* Band-10 */
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1, 0, 0, 0, 0, /* Band-11 */
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963423114, /* Post-gain */
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};
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static const u32 biquad_init_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH] = {
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23, /* Pre-shift */
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30, 30, 30, 30, 30, 0, 0, 0, 0, 0, 0, 0, /* Shift for bands */
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28, /* Post-shift */
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};
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static s32 biquad_coeff_buffer[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
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static void tegra210_peq_read_ram(struct regmap *regmap, unsigned int reg_ctrl,
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unsigned int reg_data, unsigned int ram_offset,
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unsigned int *data, size_t size)
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{
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unsigned int val;
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unsigned int i;
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val = ram_offset & TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK;
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val |= TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN;
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val |= TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN;
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val |= TEGRA210_PEQ_RAM_CTRL_RW_READ;
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regmap_write(regmap, reg_ctrl, val);
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/*
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* Since all ahub non-io modules work under same ahub clock it is not
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* necessary to check ahub read busy bit after every read.
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*/
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for (i = 0; i < size; i++)
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regmap_read(regmap, reg_data, &data[i]);
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}
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static void tegra210_peq_write_ram(struct regmap *regmap, unsigned int reg_ctrl,
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unsigned int reg_data, unsigned int ram_offset,
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unsigned int *data, size_t size)
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{
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unsigned int val;
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unsigned int i;
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val = ram_offset & TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK;
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val |= TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN;
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val |= TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN;
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val |= TEGRA210_PEQ_RAM_CTRL_RW_WRITE;
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regmap_write(regmap, reg_ctrl, val);
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for (i = 0; i < size; i++)
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regmap_write(regmap, reg_data, data[i]);
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}
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static int tegra210_peq_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int val;
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regmap_read(ope->peq_regmap, mc->reg, &val);
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ucontrol->value.integer.value[0] = (val >> mc->shift) & mask;
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if (!mc->invert)
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return 0;
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ucontrol->value.integer.value[0] =
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mc->max - ucontrol->value.integer.value[0];
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return 0;
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}
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static int tegra210_peq_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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unsigned int mask = (1 << fls(mc->max)) - 1;
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bool change = false;
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unsigned int val;
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val = (ucontrol->value.integer.value[0] & mask);
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if (mc->invert)
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val = mc->max - val;
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val = val << mc->shift;
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regmap_update_bits_check(ope->peq_regmap, mc->reg, (mask << mc->shift),
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val, &change);
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return change ? 1 : 0;
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}
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static int tegra210_peq_ram_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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u32 i, reg_ctrl = params->soc.base;
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u32 reg_data = reg_ctrl + cmpnt->val_bytes;
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s32 *data = (s32 *)biquad_coeff_buffer;
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pm_runtime_get_sync(cmpnt->dev);
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tegra210_peq_read_ram(ope->peq_regmap, reg_ctrl, reg_data,
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params->shift, data, params->soc.num_regs);
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pm_runtime_put_sync(cmpnt->dev);
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for (i = 0; i < params->soc.num_regs; i++)
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ucontrol->value.integer.value[i] = (long)data[i];
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return 0;
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}
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static int tegra210_peq_ram_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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u32 i, reg_ctrl = params->soc.base;
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u32 reg_data = reg_ctrl + cmpnt->val_bytes;
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s32 *data = (s32 *)biquad_coeff_buffer;
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for (i = 0; i < params->soc.num_regs; i++)
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data[i] = (s32)ucontrol->value.integer.value[i];
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pm_runtime_get_sync(cmpnt->dev);
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tegra210_peq_write_ram(ope->peq_regmap, reg_ctrl, reg_data,
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params->shift, data, params->soc.num_regs);
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pm_runtime_put_sync(cmpnt->dev);
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return 1;
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}
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static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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struct soc_bytes *params = (void *)kcontrol->private_value;
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->value.integer.min = INT_MIN;
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uinfo->value.integer.max = INT_MAX;
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uinfo->count = params->num_regs;
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return 0;
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}
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#define TEGRA210_PEQ_GAIN_PARAMS_CTRL(chan) \
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TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " Biquad Gain Params", \
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TEGRA210_PEQ_CFG_RAM_CTRL, \
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH, \
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(TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH * chan), 0xffffffff, \
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tegra210_peq_ram_get, tegra210_peq_ram_put, \
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tegra210_peq_param_info)
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#define TEGRA210_PEQ_SHIFT_PARAMS_CTRL(chan) \
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TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " Biquad Shift Params", \
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TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL, \
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH, \
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(TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH * chan), 0x1f, \
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tegra210_peq_ram_get, tegra210_peq_ram_put, \
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tegra210_peq_param_info)
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static const struct snd_kcontrol_new tegra210_peq_controls[] = {
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SOC_SINGLE_EXT("PEQ Active", TEGRA210_PEQ_CFG,
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TEGRA210_PEQ_CFG_MODE_SHIFT, 1, 0,
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tegra210_peq_get, tegra210_peq_put),
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SOC_SINGLE_EXT("PEQ Biquad Stages", TEGRA210_PEQ_CFG,
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TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT,
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TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0,
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tegra210_peq_get, tegra210_peq_put),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(0),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(1),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(2),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(3),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(4),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(5),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(6),
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TEGRA210_PEQ_GAIN_PARAMS_CTRL(7),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(0),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(1),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(2),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(3),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(4),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(5),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(6),
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TEGRA210_PEQ_SHIFT_PARAMS_CTRL(7),
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};
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static bool tegra210_peq_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_CG:
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case TEGRA210_PEQ_CFG ... TEGRA210_PEQ_CFG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_peq_rd_reg(struct device *dev, unsigned int reg)
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{
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if (tegra210_peq_wr_reg(dev, reg))
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return true;
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switch (reg) {
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case TEGRA210_PEQ_STATUS:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_peq_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_SOFT_RESET:
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case TEGRA210_PEQ_STATUS:
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case TEGRA210_PEQ_CFG_RAM_CTRL ... TEGRA210_PEQ_CFG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_peq_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_PEQ_CFG_RAM_DATA:
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case TEGRA210_PEQ_CFG_RAM_SHIFT_DATA:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config tegra210_peq_regmap_config = {
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.name = "peq",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
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.writeable_reg = tegra210_peq_wr_reg,
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.readable_reg = tegra210_peq_rd_reg,
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.volatile_reg = tegra210_peq_volatile_reg,
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.precious_reg = tegra210_peq_precious_reg,
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.reg_defaults = tegra210_peq_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_peq_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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void tegra210_peq_restore(struct regmap *regmap, u32 *biquad_gains,
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u32 *biquad_shifts)
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{
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unsigned int i;
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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tegra210_peq_write_ram(regmap, TEGRA210_PEQ_CFG_RAM_CTRL,
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TEGRA210_PEQ_CFG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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biquad_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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tegra210_peq_write_ram(regmap,
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TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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biquad_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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}
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void tegra210_peq_save(struct regmap *regmap, u32 *biquad_gains,
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u32 *biquad_shifts)
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{
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unsigned int i;
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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tegra210_peq_read_ram(regmap,
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TEGRA210_PEQ_CFG_RAM_CTRL,
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TEGRA210_PEQ_CFG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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biquad_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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tegra210_peq_read_ram(regmap,
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TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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biquad_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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}
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int tegra210_peq_component_init(struct snd_soc_component *cmpnt)
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{
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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unsigned int i;
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pm_runtime_get_sync(cmpnt->dev);
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regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CFG,
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TEGRA210_PEQ_CFG_MODE_MASK,
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0 << TEGRA210_PEQ_CFG_MODE_SHIFT);
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regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CFG,
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TEGRA210_PEQ_CFG_BIQUAD_STAGES_MASK,
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(TEGRA210_PEQ_BIQUAD_INIT_STAGE - 1) <<
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TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT);
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/* Initialize PEQ AHUB RAM with default params */
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for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
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/* Set default gain params */
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tegra210_peq_write_ram(ope->peq_regmap,
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TEGRA210_PEQ_CFG_RAM_CTRL,
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TEGRA210_PEQ_CFG_RAM_DATA,
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(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
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(u32 *)&biquad_init_gains,
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TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
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/* Set default shift params */
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tegra210_peq_write_ram(ope->peq_regmap,
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TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL,
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TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
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(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
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(u32 *)&biquad_init_shifts,
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TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
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}
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pm_runtime_put_sync(cmpnt->dev);
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snd_soc_add_component_controls(cmpnt, tegra210_peq_controls,
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ARRAY_SIZE(tegra210_peq_controls));
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return 0;
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}
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int tegra210_peq_regmap_init(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra210_ope *ope = dev_get_drvdata(dev);
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struct device_node *child;
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struct resource mem;
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void __iomem *regs;
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int err;
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child = of_get_child_by_name(dev->of_node, "equalizer");
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if (!child)
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return -ENODEV;
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err = of_address_to_resource(child, 0, &mem);
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of_node_put(child);
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if (err < 0) {
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dev_err(dev, "fail to get PEQ resource\n");
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return err;
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}
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mem.flags = IORESOURCE_MEM;
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regs = devm_ioremap_resource(dev, &mem);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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ope->peq_regmap = devm_regmap_init_mmio(dev, regs,
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&tegra210_peq_regmap_config);
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if (IS_ERR(ope->peq_regmap)) {
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dev_err(dev, "regmap init failed\n");
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return PTR_ERR(ope->peq_regmap);
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}
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regcache_cache_only(ope->peq_regmap, true);
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return 0;
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}
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