420 lines
11 KiB
C
420 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// tegra210_ope.c - Tegra210 OPE driver
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//
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// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra210_mbdrc.h"
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#include "tegra210_ope.h"
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#include "tegra210_peq.h"
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#include "tegra_cif.h"
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static const struct reg_default tegra210_ope_reg_defaults[] = {
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{ TEGRA210_OPE_RX_INT_MASK, 0x00000001},
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{ TEGRA210_OPE_RX_CIF_CTRL, 0x00007700},
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{ TEGRA210_OPE_TX_INT_MASK, 0x00000001},
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{ TEGRA210_OPE_TX_CIF_CTRL, 0x00007700},
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{ TEGRA210_OPE_CG, 0x1},
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};
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static int tegra210_ope_set_audio_cif(struct tegra210_ope *ope,
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struct snd_pcm_hw_params *params,
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unsigned int reg)
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{
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int channels, audio_bits;
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struct tegra_cif_conf cif_conf;
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
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channels = params_channels(params);
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if (channels < 2)
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return -EINVAL;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA_ACIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA_ACIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.audio_ch = channels;
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cif_conf.client_ch = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra_set_cif(ope->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_ope_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_ope *ope = snd_soc_dai_get_drvdata(dai);
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int err;
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/* Set RX and TX CIF */
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err = tegra210_ope_set_audio_cif(ope, params,
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TEGRA210_OPE_RX_CIF_CTRL);
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if (err) {
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dev_err(dev, "Can't set OPE RX CIF: %d\n", err);
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return err;
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}
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err = tegra210_ope_set_audio_cif(ope, params,
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TEGRA210_OPE_TX_CIF_CTRL);
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if (err) {
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dev_err(dev, "Can't set OPE TX CIF: %d\n", err);
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return err;
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}
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tegra210_mbdrc_hw_params(dai->component);
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return err;
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}
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static int tegra210_ope_component_probe(struct snd_soc_component *cmpnt)
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{
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struct tegra210_ope *ope = dev_get_drvdata(cmpnt->dev);
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tegra210_peq_component_init(cmpnt);
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tegra210_mbdrc_component_init(cmpnt);
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/*
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* The OPE, PEQ and MBDRC functionalities are combined under one
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* device registered by OPE driver. In fact OPE HW block includes
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* sub blocks PEQ and MBDRC. However driver registers separate
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* regmap interfaces for each of these. ASoC core depends on
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* dev_get_regmap() to populate the regmap field for a given ASoC
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* component. A component can have one regmap reference and since
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* the DAPM routes depend on OPE regmap only, below explicit
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* assignment is done to highlight this. This is needed for ASoC
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* core to access correct regmap during DAPM path setup.
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*/
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snd_soc_component_init_regmap(cmpnt, ope->regmap);
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return 0;
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}
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static const struct snd_soc_dai_ops tegra210_ope_dai_ops = {
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.hw_params = tegra210_ope_hw_params,
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};
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static struct snd_soc_dai_driver tegra210_ope_dais[] = {
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{
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.name = "OPE-RX-CIF",
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.playback = {
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.stream_name = "RX-CIF-Playback",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.capture = {
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.stream_name = "RX-CIF-Capture",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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},
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{
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.name = "OPE-TX-CIF",
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.playback = {
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.stream_name = "TX-CIF-Playback",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.capture = {
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.stream_name = "TX-CIF-Capture",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.ops = &tegra210_ope_dai_ops,
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}
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};
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static const struct snd_soc_dapm_widget tegra210_ope_widgets[] = {
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SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_OPE_ENABLE,
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TEGRA210_OPE_EN_SHIFT, 0),
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};
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#define OPE_ROUTES(sname) \
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{ "RX XBAR-" sname, NULL, "XBAR-TX" }, \
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{ "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \
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{ "RX", NULL, "RX-CIF-" sname }, \
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{ "TX-CIF-" sname, NULL, "TX" }, \
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{ "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \
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{ "XBAR-RX", NULL, "TX XBAR-" sname }
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static const struct snd_soc_dapm_route tegra210_ope_routes[] = {
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{ "TX", NULL, "RX" },
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OPE_ROUTES("Playback"),
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OPE_ROUTES("Capture"),
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};
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static const char * const tegra210_ope_data_dir_text[] = {
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"MBDRC to PEQ",
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"PEQ to MBDRC"
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};
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static const struct soc_enum tegra210_ope_data_dir_enum =
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SOC_ENUM_SINGLE(TEGRA210_OPE_DIR, TEGRA210_OPE_DIR_SHIFT,
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2, tegra210_ope_data_dir_text);
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static int tegra210_ope_get_data_dir(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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ucontrol->value.enumerated.item[0] = ope->data_dir;
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return 0;
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}
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static int tegra210_ope_put_data_dir(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
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unsigned int value = ucontrol->value.enumerated.item[0];
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if (value == ope->data_dir)
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return 0;
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ope->data_dir = value;
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return 1;
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}
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static const struct snd_kcontrol_new tegra210_ope_controls[] = {
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SOC_ENUM_EXT("Data Flow Direction", tegra210_ope_data_dir_enum,
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tegra210_ope_get_data_dir, tegra210_ope_put_data_dir),
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};
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static const struct snd_soc_component_driver tegra210_ope_cmpnt = {
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.probe = tegra210_ope_component_probe,
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.dapm_widgets = tegra210_ope_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_ope_widgets),
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.dapm_routes = tegra210_ope_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_ope_routes),
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.controls = tegra210_ope_controls,
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.num_controls = ARRAY_SIZE(tegra210_ope_controls),
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};
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static bool tegra210_ope_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_OPE_RX_INT_MASK ... TEGRA210_OPE_RX_CIF_CTRL:
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case TEGRA210_OPE_TX_INT_MASK ... TEGRA210_OPE_TX_CIF_CTRL:
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case TEGRA210_OPE_ENABLE ... TEGRA210_OPE_CG:
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case TEGRA210_OPE_DIR:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_ope_rd_reg(struct device *dev, unsigned int reg)
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{
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if (tegra210_ope_wr_reg(dev, reg))
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return true;
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switch (reg) {
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case TEGRA210_OPE_RX_STATUS:
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case TEGRA210_OPE_RX_INT_STATUS:
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case TEGRA210_OPE_TX_STATUS:
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case TEGRA210_OPE_TX_INT_STATUS:
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case TEGRA210_OPE_STATUS:
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case TEGRA210_OPE_INT_STATUS:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_ope_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_OPE_RX_STATUS:
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case TEGRA210_OPE_RX_INT_STATUS:
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case TEGRA210_OPE_TX_STATUS:
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case TEGRA210_OPE_TX_INT_STATUS:
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case TEGRA210_OPE_SOFT_RESET:
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case TEGRA210_OPE_STATUS:
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case TEGRA210_OPE_INT_STATUS:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config tegra210_ope_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_OPE_DIR,
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.writeable_reg = tegra210_ope_wr_reg,
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.readable_reg = tegra210_ope_rd_reg,
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.volatile_reg = tegra210_ope_volatile_reg,
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.reg_defaults = tegra210_ope_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_ope_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static int tegra210_ope_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra210_ope *ope;
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void __iomem *regs;
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int err;
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ope = devm_kzalloc(dev, sizeof(*ope), GFP_KERNEL);
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if (!ope)
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return -ENOMEM;
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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ope->regmap = devm_regmap_init_mmio(dev, regs,
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&tegra210_ope_regmap_config);
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if (IS_ERR(ope->regmap)) {
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dev_err(dev, "regmap init failed\n");
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return PTR_ERR(ope->regmap);
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}
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regcache_cache_only(ope->regmap, true);
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dev_set_drvdata(dev, ope);
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err = tegra210_peq_regmap_init(pdev);
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if (err < 0) {
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dev_err(dev, "PEQ init failed\n");
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return err;
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}
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err = tegra210_mbdrc_regmap_init(pdev);
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if (err < 0) {
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dev_err(dev, "MBDRC init failed\n");
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return err;
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}
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err = devm_snd_soc_register_component(dev, &tegra210_ope_cmpnt,
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tegra210_ope_dais,
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ARRAY_SIZE(tegra210_ope_dais));
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if (err) {
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dev_err(dev, "can't register OPE component, err: %d\n", err);
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return err;
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}
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pm_runtime_enable(dev);
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return 0;
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}
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static int tegra210_ope_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static int __maybe_unused tegra210_ope_runtime_suspend(struct device *dev)
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{
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struct tegra210_ope *ope = dev_get_drvdata(dev);
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tegra210_peq_save(ope->peq_regmap, ope->peq_biquad_gains,
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ope->peq_biquad_shifts);
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regcache_cache_only(ope->mbdrc_regmap, true);
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regcache_cache_only(ope->peq_regmap, true);
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regcache_cache_only(ope->regmap, true);
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regcache_mark_dirty(ope->regmap);
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regcache_mark_dirty(ope->peq_regmap);
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regcache_mark_dirty(ope->mbdrc_regmap);
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return 0;
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}
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static int __maybe_unused tegra210_ope_runtime_resume(struct device *dev)
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{
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struct tegra210_ope *ope = dev_get_drvdata(dev);
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regcache_cache_only(ope->regmap, false);
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regcache_cache_only(ope->peq_regmap, false);
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regcache_cache_only(ope->mbdrc_regmap, false);
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regcache_sync(ope->regmap);
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regcache_sync(ope->peq_regmap);
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regcache_sync(ope->mbdrc_regmap);
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tegra210_peq_restore(ope->peq_regmap, ope->peq_biquad_gains,
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ope->peq_biquad_shifts);
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return 0;
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}
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static const struct dev_pm_ops tegra210_ope_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra210_ope_runtime_suspend,
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tegra210_ope_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct of_device_id tegra210_ope_of_match[] = {
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{ .compatible = "nvidia,tegra210-ope" },
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{},
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};
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MODULE_DEVICE_TABLE(of, tegra210_ope_of_match);
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static struct platform_driver tegra210_ope_driver = {
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.driver = {
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.name = "tegra210-ope",
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.of_match_table = tegra210_ope_of_match,
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.pm = &tegra210_ope_pm_ops,
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},
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.probe = tegra210_ope_probe,
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.remove = tegra210_ope_remove,
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};
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module_platform_driver(tegra210_ope_driver)
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MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
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MODULE_DESCRIPTION("Tegra210 OPE ASoC driver");
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MODULE_LICENSE("GPL");
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