433 lines
11 KiB
C
433 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* tegra20_spdif.c - Tegra20 SPDIF driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2011-2012 - NVIDIA, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "tegra20_spdif.h"
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static __maybe_unused int tegra20_spdif_runtime_suspend(struct device *dev)
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{
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struct tegra20_spdif *spdif = dev_get_drvdata(dev);
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regcache_cache_only(spdif->regmap, true);
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clk_disable_unprepare(spdif->clk_spdif_out);
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return 0;
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}
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static __maybe_unused int tegra20_spdif_runtime_resume(struct device *dev)
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{
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struct tegra20_spdif *spdif = dev_get_drvdata(dev);
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int ret;
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ret = reset_control_assert(spdif->reset);
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if (ret)
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return ret;
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ret = clk_prepare_enable(spdif->clk_spdif_out);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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usleep_range(10, 100);
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ret = reset_control_deassert(spdif->reset);
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if (ret)
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goto disable_clocks;
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regcache_cache_only(spdif->regmap, false);
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regcache_mark_dirty(spdif->regmap);
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ret = regcache_sync(spdif->regmap);
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if (ret)
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goto disable_clocks;
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return 0;
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disable_clocks:
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clk_disable_unprepare(spdif->clk_spdif_out);
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return ret;
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}
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static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
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unsigned int mask = 0, val = 0;
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int ret, spdifclock;
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long rate;
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mask |= TEGRA20_SPDIF_CTRL_PACK |
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TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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val |= TEGRA20_SPDIF_CTRL_PACK |
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TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
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/*
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* FIFO trigger level must be bigger than DMA burst or equal to it,
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* otherwise data is discarded on overflow.
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*/
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
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TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK,
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TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL);
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switch (params_rate(params)) {
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case 32000:
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spdifclock = 4096000;
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break;
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case 44100:
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spdifclock = 5644800;
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break;
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case 48000:
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spdifclock = 6144000;
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break;
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case 88200:
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spdifclock = 11289600;
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break;
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case 96000:
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spdifclock = 12288000;
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break;
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case 176400:
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spdifclock = 22579200;
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break;
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case 192000:
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spdifclock = 24576000;
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break;
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default:
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return -EINVAL;
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}
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ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
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if (ret) {
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dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret);
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return ret;
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}
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rate = clk_get_rate(spdif->clk_spdif_out);
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if (rate != spdifclock)
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dev_warn_once(dai->dev,
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"SPDIF clock rate %d doesn't match requested rate %lu\n",
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spdifclock, rate);
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return 0;
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}
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static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
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{
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
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TEGRA20_SPDIF_CTRL_TX_EN,
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TEGRA20_SPDIF_CTRL_TX_EN);
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}
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static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
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{
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
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TEGRA20_SPDIF_CTRL_TX_EN, 0);
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}
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static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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tegra20_spdif_start_playback(spdif);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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tegra20_spdif_stop_playback(spdif);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int tegra20_spdif_filter_rates(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct snd_interval *r = hw_param_interval(params, rule->var);
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struct snd_soc_dai *dai = rule->private;
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struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
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struct clk *parent = clk_get_parent(spdif->clk_spdif_out);
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static const unsigned int rates[] = { 32000, 44100, 48000 };
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long i, parent_rate, valid_rates = 0;
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parent_rate = clk_get_rate(parent);
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if (parent_rate <= 0) {
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dev_err(dai->dev, "Can't get parent clock rate: %ld\n",
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parent_rate);
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return parent_rate ?: -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(rates); i++) {
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if (parent_rate % (rates[i] * 128) == 0)
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valid_rates |= BIT(i);
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}
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/*
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* At least one rate must be valid, otherwise the parent clock isn't
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* audio PLL. Nothing should be filtered in this case.
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*/
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if (!valid_rates)
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valid_rates = BIT(ARRAY_SIZE(rates)) - 1;
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return snd_interval_list(r, ARRAY_SIZE(rates), rates, valid_rates);
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}
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static int tegra20_spdif_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
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return 0;
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/*
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* SPDIF and I2S share audio PLL. HDMI takes audio packets from SPDIF
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* and audio may not work on some TVs if clock rate isn't precise.
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*
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* PLL rate is controlled by I2S side. Filter out audio rates that
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* don't match PLL rate at the start of stream to allow both SPDIF
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* and I2S work simultaneously, assuming that PLL rate won't be
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* changed later on.
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*/
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return snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE,
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tegra20_spdif_filter_rates, dai,
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SNDRV_PCM_HW_PARAM_RATE, -1);
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}
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static int tegra20_spdif_probe(struct snd_soc_dai *dai)
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{
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struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
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dai->capture_dma_data = NULL;
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dai->playback_dma_data = &spdif->playback_dma_data;
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return 0;
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}
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static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
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.hw_params = tegra20_spdif_hw_params,
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.trigger = tegra20_spdif_trigger,
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.startup = tegra20_spdif_startup,
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};
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static struct snd_soc_dai_driver tegra20_spdif_dai = {
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.name = "tegra20-spdif",
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.probe = tegra20_spdif_probe,
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.playback = {
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.stream_name = "Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra20_spdif_dai_ops,
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};
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static const struct snd_soc_component_driver tegra20_spdif_component = {
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.name = "tegra20-spdif",
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.legacy_dai_naming = 1,
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};
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static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_SPDIF_CTRL:
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case TEGRA20_SPDIF_STATUS:
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case TEGRA20_SPDIF_STROBE_CTRL:
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case TEGRA20_SPDIF_DATA_FIFO_CSR:
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case TEGRA20_SPDIF_DATA_OUT:
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case TEGRA20_SPDIF_DATA_IN:
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case TEGRA20_SPDIF_CH_STA_RX_A:
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case TEGRA20_SPDIF_CH_STA_RX_B:
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case TEGRA20_SPDIF_CH_STA_RX_C:
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case TEGRA20_SPDIF_CH_STA_RX_D:
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case TEGRA20_SPDIF_CH_STA_RX_E:
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case TEGRA20_SPDIF_CH_STA_RX_F:
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case TEGRA20_SPDIF_CH_STA_TX_A:
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case TEGRA20_SPDIF_CH_STA_TX_B:
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case TEGRA20_SPDIF_CH_STA_TX_C:
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case TEGRA20_SPDIF_CH_STA_TX_D:
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case TEGRA20_SPDIF_CH_STA_TX_E:
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case TEGRA20_SPDIF_CH_STA_TX_F:
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case TEGRA20_SPDIF_USR_STA_RX_A:
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case TEGRA20_SPDIF_USR_DAT_TX_A:
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return true;
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default:
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return false;
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}
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}
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static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_SPDIF_STATUS:
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case TEGRA20_SPDIF_DATA_FIFO_CSR:
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case TEGRA20_SPDIF_DATA_OUT:
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case TEGRA20_SPDIF_DATA_IN:
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case TEGRA20_SPDIF_CH_STA_RX_A:
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case TEGRA20_SPDIF_CH_STA_RX_B:
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case TEGRA20_SPDIF_CH_STA_RX_C:
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case TEGRA20_SPDIF_CH_STA_RX_D:
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case TEGRA20_SPDIF_CH_STA_RX_E:
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case TEGRA20_SPDIF_CH_STA_RX_F:
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case TEGRA20_SPDIF_USR_STA_RX_A:
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case TEGRA20_SPDIF_USR_DAT_TX_A:
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return true;
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default:
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return false;
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}
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}
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static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_SPDIF_DATA_OUT:
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case TEGRA20_SPDIF_DATA_IN:
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case TEGRA20_SPDIF_USR_STA_RX_A:
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case TEGRA20_SPDIF_USR_DAT_TX_A:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config tegra20_spdif_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
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.writeable_reg = tegra20_spdif_wr_rd_reg,
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.readable_reg = tegra20_spdif_wr_rd_reg,
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.volatile_reg = tegra20_spdif_volatile_reg,
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.precious_reg = tegra20_spdif_precious_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int tegra20_spdif_platform_probe(struct platform_device *pdev)
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{
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struct tegra20_spdif *spdif;
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struct resource *mem;
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void __iomem *regs;
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int ret;
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spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
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GFP_KERNEL);
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if (!spdif)
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return -ENOMEM;
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dev_set_drvdata(&pdev->dev, spdif);
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spdif->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(spdif->reset)) {
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dev_err(&pdev->dev, "Can't retrieve spdif reset\n");
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return PTR_ERR(spdif->reset);
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}
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spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out");
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if (IS_ERR(spdif->clk_spdif_out)) {
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dev_err(&pdev->dev, "Could not retrieve spdif clock\n");
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return PTR_ERR(spdif->clk_spdif_out);
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}
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regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra20_spdif_regmap_config);
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if (IS_ERR(spdif->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(spdif->regmap);
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}
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spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
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spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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spdif->playback_dma_data.maxburst = 4;
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ret = devm_pm_runtime_enable(&pdev->dev);
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if (ret)
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return ret;
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ret = devm_snd_soc_register_component(&pdev->dev,
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&tegra20_spdif_component,
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&tegra20_spdif_dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
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return ret;
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}
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ret = devm_tegra_pcm_platform_register(&pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct dev_pm_ops tegra20_spdif_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
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tegra20_spdif_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct of_device_id tegra20_spdif_of_match[] = {
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{ .compatible = "nvidia,tegra20-spdif", },
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{},
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};
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MODULE_DEVICE_TABLE(of, tegra20_spdif_of_match);
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static struct platform_driver tegra20_spdif_driver = {
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.driver = {
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.name = "tegra20-spdif",
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.pm = &tegra20_spdif_pm_ops,
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.of_match_table = tegra20_spdif_of_match,
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},
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.probe = tegra20_spdif_platform_probe,
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};
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module_platform_driver(tegra20_spdif_driver);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
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MODULE_LICENSE("GPL");
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