555 lines
15 KiB
C
555 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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//
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// tegra186_dspk.c - Tegra186 DSPK driver
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra186_dspk.h"
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#include "tegra_cif.h"
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static const struct reg_default tegra186_dspk_reg_defaults[] = {
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{ TEGRA186_DSPK_RX_INT_MASK, 0x00000007 },
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{ TEGRA186_DSPK_RX_CIF_CTRL, 0x00007700 },
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{ TEGRA186_DSPK_CG, 0x00000001 },
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{ TEGRA186_DSPK_CORE_CTRL, 0x00000310 },
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{ TEGRA186_DSPK_CODEC_CTRL, 0x03000000 },
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};
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static int tegra186_dspk_get_fifo_th(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
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return 0;
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}
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static int tegra186_dspk_put_fifo_th(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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int value = ucontrol->value.integer.value[0];
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if (value == dspk->rx_fifo_th)
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return 0;
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dspk->rx_fifo_th = value;
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return 1;
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}
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static int tegra186_dspk_get_osr_val(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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ucontrol->value.enumerated.item[0] = dspk->osr_val;
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return 0;
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}
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static int tegra186_dspk_put_osr_val(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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unsigned int value = ucontrol->value.enumerated.item[0];
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if (value == dspk->osr_val)
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return 0;
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dspk->osr_val = value;
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return 1;
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}
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static int tegra186_dspk_get_pol_sel(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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ucontrol->value.enumerated.item[0] = dspk->lrsel;
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return 0;
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}
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static int tegra186_dspk_put_pol_sel(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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unsigned int value = ucontrol->value.enumerated.item[0];
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if (value == dspk->lrsel)
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return 0;
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dspk->lrsel = value;
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return 1;
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}
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static int tegra186_dspk_get_ch_sel(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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ucontrol->value.enumerated.item[0] = dspk->ch_sel;
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return 0;
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}
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static int tegra186_dspk_put_ch_sel(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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unsigned int value = ucontrol->value.enumerated.item[0];
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if (value == dspk->ch_sel)
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return 0;
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dspk->ch_sel = value;
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return 1;
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}
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static int tegra186_dspk_get_mono_to_stereo(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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ucontrol->value.enumerated.item[0] = dspk->mono_to_stereo;
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return 0;
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}
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static int tegra186_dspk_put_mono_to_stereo(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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unsigned int value = ucontrol->value.enumerated.item[0];
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if (value == dspk->mono_to_stereo)
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return 0;
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dspk->mono_to_stereo = value;
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return 1;
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}
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static int tegra186_dspk_get_stereo_to_mono(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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ucontrol->value.enumerated.item[0] = dspk->stereo_to_mono;
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return 0;
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}
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static int tegra186_dspk_put_stereo_to_mono(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
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struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
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unsigned int value = ucontrol->value.enumerated.item[0];
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if (value == dspk->stereo_to_mono)
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return 0;
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dspk->stereo_to_mono = value;
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return 1;
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}
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static int __maybe_unused tegra186_dspk_runtime_suspend(struct device *dev)
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{
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struct tegra186_dspk *dspk = dev_get_drvdata(dev);
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regcache_cache_only(dspk->regmap, true);
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regcache_mark_dirty(dspk->regmap);
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clk_disable_unprepare(dspk->clk_dspk);
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return 0;
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}
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static int __maybe_unused tegra186_dspk_runtime_resume(struct device *dev)
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{
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struct tegra186_dspk *dspk = dev_get_drvdata(dev);
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int err;
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err = clk_prepare_enable(dspk->clk_dspk);
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if (err) {
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dev_err(dev, "failed to enable DSPK clock, err: %d\n", err);
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return err;
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}
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regcache_cache_only(dspk->regmap, false);
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regcache_sync(dspk->regmap);
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return 0;
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}
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static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
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unsigned int channels, srate, dspk_clk;
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struct device *dev = dai->dev;
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struct tegra_cif_conf cif_conf;
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unsigned int max_th;
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int err;
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
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channels = params_channels(params);
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cif_conf.audio_ch = channels;
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/* Client channel */
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switch (dspk->ch_sel) {
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case DSPK_CH_SELECT_LEFT:
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case DSPK_CH_SELECT_RIGHT:
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cif_conf.client_ch = 1;
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break;
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case DSPK_CH_SELECT_STEREO:
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cif_conf.client_ch = 2;
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break;
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default:
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dev_err(dev, "Invalid DSPK client channels\n");
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return -EINVAL;
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}
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
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cif_conf.client_bits = TEGRA_ACIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
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cif_conf.client_bits = TEGRA_ACIF_BITS_24;
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break;
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default:
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dev_err(dev, "unsupported format!\n");
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return -EOPNOTSUPP;
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}
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srate = params_rate(params);
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/* RX FIFO threshold in terms of frames */
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max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
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if (dspk->rx_fifo_th > max_th)
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dspk->rx_fifo_th = max_th;
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cif_conf.threshold = dspk->rx_fifo_th;
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cif_conf.mono_conv = dspk->mono_to_stereo;
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cif_conf.stereo_conv = dspk->stereo_to_mono;
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tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,
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&cif_conf);
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/*
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* DSPK clock and PDM codec clock should be synchronous with 4:1 ratio,
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* this is because it takes 4 clock cycles to send out one sample to
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* codec by sigma delta modulator. Finally the clock rate is a multiple
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* of 'Over Sampling Ratio', 'Sample Rate' and 'Interface Clock Ratio'.
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*/
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dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;
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err = clk_set_rate(dspk->clk_dspk, dspk_clk);
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if (err) {
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dev_err(dev, "can't set DSPK clock rate %u, err: %d\n",
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dspk_clk, err);
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return err;
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}
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regmap_update_bits(dspk->regmap,
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/* Reg */
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TEGRA186_DSPK_CORE_CTRL,
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/* Mask */
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TEGRA186_DSPK_OSR_MASK |
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TEGRA186_DSPK_CHANNEL_SELECT_MASK |
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TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK,
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/* Value */
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(dspk->osr_val << DSPK_OSR_SHIFT) |
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((dspk->ch_sel + 1) << CH_SEL_SHIFT) |
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(dspk->lrsel << LRSEL_POL_SHIFT));
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return 0;
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}
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static const struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
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.hw_params = tegra186_dspk_hw_params,
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};
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static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
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{
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.name = "DSPK-CIF",
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.playback = {
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.stream_name = "CIF-Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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},
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{
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.name = "DSPK-DAP",
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.playback = {
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.stream_name = "DAP-Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.ops = &tegra186_dspk_dai_ops,
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.symmetric_rate = 1,
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},
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};
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static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = {
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SND_SOC_DAPM_AIF_IN("RX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0),
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SND_SOC_DAPM_SPK("SPK", NULL),
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};
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static const struct snd_soc_dapm_route tegra186_dspk_routes[] = {
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{ "XBAR-Playback", NULL, "XBAR-TX" },
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{ "CIF-Playback", NULL, "XBAR-Playback" },
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{ "RX", NULL, "CIF-Playback" },
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{ "DAP-Playback", NULL, "RX" },
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{ "SPK", NULL, "DAP-Playback" },
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};
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static const char * const tegra186_dspk_ch_sel_text[] = {
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"Left", "Right", "Stereo",
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};
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static const struct soc_enum tegra186_dspk_ch_sel_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_ch_sel_text),
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tegra186_dspk_ch_sel_text);
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static const char * const tegra186_dspk_osr_text[] = {
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"OSR_32", "OSR_64", "OSR_128", "OSR_256",
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};
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static const struct soc_enum tegra186_dspk_osr_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_osr_text),
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tegra186_dspk_osr_text);
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static const char * const tegra186_dspk_lrsel_text[] = {
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"Left", "Right",
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};
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static const char * const tegra186_dspk_mono_conv_text[] = {
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"Zero", "Copy",
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};
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static const struct soc_enum tegra186_dspk_mono_conv_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
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ARRAY_SIZE(tegra186_dspk_mono_conv_text),
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tegra186_dspk_mono_conv_text);
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static const char * const tegra186_dspk_stereo_conv_text[] = {
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"CH0", "CH1", "AVG",
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};
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static const struct soc_enum tegra186_dspk_stereo_conv_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
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ARRAY_SIZE(tegra186_dspk_stereo_conv_text),
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tegra186_dspk_stereo_conv_text);
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static const struct soc_enum tegra186_dspk_lrsel_enum =
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SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_lrsel_text),
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tegra186_dspk_lrsel_text);
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static const struct snd_kcontrol_new tegrat186_dspk_controls[] = {
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SOC_SINGLE_EXT("FIFO Threshold", SND_SOC_NOPM, 0,
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TEGRA186_DSPK_RX_FIFO_DEPTH - 1, 0,
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tegra186_dspk_get_fifo_th, tegra186_dspk_put_fifo_th),
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SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum,
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tegra186_dspk_get_osr_val, tegra186_dspk_put_osr_val),
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SOC_ENUM_EXT("LR Polarity Select", tegra186_dspk_lrsel_enum,
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tegra186_dspk_get_pol_sel, tegra186_dspk_put_pol_sel),
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SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum,
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tegra186_dspk_get_ch_sel, tegra186_dspk_put_ch_sel),
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SOC_ENUM_EXT("Mono To Stereo", tegra186_dspk_mono_conv_enum,
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tegra186_dspk_get_mono_to_stereo,
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tegra186_dspk_put_mono_to_stereo),
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SOC_ENUM_EXT("Stereo To Mono", tegra186_dspk_stereo_conv_enum,
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tegra186_dspk_get_stereo_to_mono,
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tegra186_dspk_put_stereo_to_mono),
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};
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static const struct snd_soc_component_driver tegra186_dspk_cmpnt = {
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.dapm_widgets = tegra186_dspk_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
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.dapm_routes = tegra186_dspk_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
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.controls = tegrat186_dspk_controls,
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.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
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};
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static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA186_DSPK_RX_INT_MASK ... TEGRA186_DSPK_RX_CIF_CTRL:
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case TEGRA186_DSPK_ENABLE ... TEGRA186_DSPK_CG:
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case TEGRA186_DSPK_CORE_CTRL ... TEGRA186_DSPK_CODEC_CTRL:
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return true;
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default:
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return false;
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}
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}
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static bool tegra186_dspk_rd_reg(struct device *dev, unsigned int reg)
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{
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if (tegra186_dspk_wr_reg(dev, reg))
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return true;
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switch (reg) {
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case TEGRA186_DSPK_RX_STATUS:
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case TEGRA186_DSPK_RX_INT_STATUS:
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case TEGRA186_DSPK_STATUS:
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case TEGRA186_DSPK_INT_STATUS:
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return true;
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default:
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return false;
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}
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}
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static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA186_DSPK_RX_STATUS:
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case TEGRA186_DSPK_RX_INT_STATUS:
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case TEGRA186_DSPK_STATUS:
|
|
case TEGRA186_DSPK_INT_STATUS:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static const struct regmap_config tegra186_dspk_regmap = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA186_DSPK_CODEC_CTRL,
|
|
.writeable_reg = tegra186_dspk_wr_reg,
|
|
.readable_reg = tegra186_dspk_rd_reg,
|
|
.volatile_reg = tegra186_dspk_volatile_reg,
|
|
.reg_defaults = tegra186_dspk_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults),
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static const struct of_device_id tegra186_dspk_of_match[] = {
|
|
{ .compatible = "nvidia,tegra186-dspk" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
|
|
|
|
static int tegra186_dspk_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct tegra186_dspk *dspk;
|
|
void __iomem *regs;
|
|
int err;
|
|
|
|
dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);
|
|
if (!dspk)
|
|
return -ENOMEM;
|
|
|
|
dspk->osr_val = DSPK_OSR_64;
|
|
dspk->lrsel = DSPK_LRSEL_LEFT;
|
|
dspk->ch_sel = DSPK_CH_SELECT_STEREO;
|
|
dspk->mono_to_stereo = 0; /* "Zero" */
|
|
|
|
dev_set_drvdata(dev, dspk);
|
|
|
|
dspk->clk_dspk = devm_clk_get(dev, "dspk");
|
|
if (IS_ERR(dspk->clk_dspk)) {
|
|
dev_err(dev, "can't retrieve DSPK clock\n");
|
|
return PTR_ERR(dspk->clk_dspk);
|
|
}
|
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);
|
|
if (IS_ERR(dspk->regmap)) {
|
|
dev_err(dev, "regmap init failed\n");
|
|
return PTR_ERR(dspk->regmap);
|
|
}
|
|
|
|
regcache_cache_only(dspk->regmap, true);
|
|
|
|
err = devm_snd_soc_register_component(dev, &tegra186_dspk_cmpnt,
|
|
tegra186_dspk_dais,
|
|
ARRAY_SIZE(tegra186_dspk_dais));
|
|
if (err) {
|
|
dev_err(dev, "can't register DSPK component, err: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra186_dspk_platform_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra186_dspk_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend,
|
|
tegra186_dspk_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra186_dspk_driver = {
|
|
.driver = {
|
|
.name = "tegra186-dspk",
|
|
.of_match_table = tegra186_dspk_of_match,
|
|
.pm = &tegra186_dspk_pm_ops,
|
|
},
|
|
.probe = tegra186_dspk_platform_probe,
|
|
.remove = tegra186_dspk_platform_remove,
|
|
};
|
|
module_platform_driver(tegra186_dspk_driver);
|
|
|
|
MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
|
|
MODULE_AUTHOR("Sameer Pujar <spujar@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra186 ASoC DSPK driver");
|
|
MODULE_LICENSE("GPL v2");
|