255 lines
7.7 KiB
C
255 lines
7.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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*/
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#ifndef __SOF_AMD_ACP_H
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#define __SOF_AMD_ACP_H
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#include "../sof-priv.h"
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#define ACP_MAX_STREAM 8
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#define ACP_DSP_BAR 0
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#define ACP_HW_SEM_RETRY_COUNT 10000
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#define ACP_REG_POLL_INTERVAL 500
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#define ACP_REG_POLL_TIMEOUT_US 2000
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#define ACP_DMA_COMPLETE_TIMEOUT_US 5000
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
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#define ACP_PGFSM_STATUS_MASK 0x03
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#define ACP_POWERED_ON 0x00
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#define ACP_ASSERT_RESET 0x01
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#define ACP_RELEASE_RESET 0x00
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#define ACP_SOFT_RESET_DONE_MASK 0x00010001
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#define ACP_DSP_INTR_EN_MASK 0x00000001
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#define ACP3X_SRAM_PTE_OFFSET 0x02050000
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#define ACP6X_SRAM_PTE_OFFSET 0x03800000
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define ACP_PAGE_SIZE 0x1000
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#define ACP_DMA_CH_RUN 0x02
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#define ACP_MAX_DESC_CNT 0x02
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#define DSP_FW_RUN_ENABLE 0x01
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#define ACP_SHA_RUN 0x01
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#define ACP_SHA_RESET 0x02
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#define ACP_DMA_CH_RST 0x01
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#define ACP_DMA_CH_GRACEFUL_RST_EN 0x10
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#define ACP_ATU_CACHE_INVALID 0x01
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#define ACP_MAX_DESC 128
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#define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0
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#define ACP_DEFAULT_DRAM_LENGTH 0x00080000
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#define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000
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#define ACP_SYSTEM_MEMORY_WINDOW 0x4000000
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#define ACP_IRAM_BASE_ADDRESS 0x000000
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#define ACP_DATA_RAM_BASE_ADDRESS 0x01000000
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#define ACP_DRAM_PAGE_COUNT 128
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#define ACP_DSP_TO_HOST_IRQ 0x04
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#define ACP_RN_PCI_ID 0x01
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#define ACP_RMB_PCI_ID 0x6F
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#define HOST_BRIDGE_CZN 0x1630
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#define HOST_BRIDGE_RMB 0x14B5
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#define ACP_SHA_STAT 0x8000
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#define ACP_PSP_TIMEOUT_COUNTER 5
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#define ACP_EXT_INTR_ERROR_STAT 0x20000000
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#define MP0_C2PMSG_114_REG 0x3810AC8
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#define MP0_C2PMSG_73_REG 0x3810A24
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#define MBOX_ACP_SHA_DMA_COMMAND 0x70000
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#define MBOX_DELAY 1000
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#define MBOX_READY_MASK 0x80000000
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#define MBOX_STATUS_MASK 0xFFFF
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#define BOX_SIZE_512 0x200
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#define BOX_SIZE_1024 0x400
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struct acp_atu_grp_pte {
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u32 low;
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u32 high;
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};
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union dma_tx_cnt {
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struct {
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unsigned int count : 19;
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unsigned int reserved : 12;
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unsigned ioc : 1;
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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};
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struct dma_descriptor {
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unsigned int src_addr;
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unsigned int dest_addr;
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union dma_tx_cnt tx_cnt;
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unsigned int reserved;
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};
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/* Scratch memory structure for communication b/w host and dsp */
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struct scratch_ipc_conf {
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/* Debug memory */
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u8 sof_debug_box[1024];
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/* Exception memory*/
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u8 sof_except_box[1024];
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/* Stream buffer */
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u8 sof_stream_box[1024];
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/* Trace buffer */
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u8 sof_trace_box[1024];
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/* Host msg flag */
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u32 sof_host_msg_write;
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/* Host ack flag*/
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u32 sof_host_ack_write;
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/* DSP msg flag */
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u32 sof_dsp_msg_write;
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/* Dsp ack flag */
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u32 sof_dsp_ack_write;
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};
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struct scratch_reg_conf {
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struct scratch_ipc_conf info;
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struct acp_atu_grp_pte grp1_pte[16];
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struct acp_atu_grp_pte grp2_pte[16];
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struct acp_atu_grp_pte grp3_pte[16];
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struct acp_atu_grp_pte grp4_pte[16];
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struct acp_atu_grp_pte grp5_pte[16];
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struct acp_atu_grp_pte grp6_pte[16];
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struct acp_atu_grp_pte grp7_pte[16];
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struct acp_atu_grp_pte grp8_pte[16];
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struct dma_descriptor dma_desc[64];
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unsigned int reg_offset[8];
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unsigned int buf_size[8];
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u8 acp_tx_fifo_buf[256];
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u8 acp_rx_fifo_buf[256];
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unsigned int reserve[];
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};
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struct acp_dsp_stream {
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struct list_head list;
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struct snd_sof_dev *sdev;
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struct snd_pcm_substream *substream;
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struct snd_dma_buffer *dmab;
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int num_pages;
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int stream_tag;
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int active;
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unsigned int reg_offset;
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};
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struct sof_amd_acp_desc {
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unsigned int rev;
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unsigned int host_bridge_id;
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unsigned int i2s_mode;
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u32 pgfsm_base;
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u32 ext_intr_stat;
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u32 dsp_intr_base;
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u32 sram_pte_offset;
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u32 i2s_pin_config_offset;
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u32 hw_semaphore_offset;
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u32 acp_clkmux_sel;
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u32 fusion_dsp_offset;
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};
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/* Common device data struct for ACP devices */
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struct acp_dev_data {
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struct snd_sof_dev *dev;
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unsigned int fw_bin_size;
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unsigned int fw_data_bin_size;
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u32 fw_bin_page_count;
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dma_addr_t sha_dma_addr;
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u8 *bin_buf;
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dma_addr_t dma_addr;
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u8 *data_buf;
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struct dma_descriptor dscr_info[ACP_MAX_DESC];
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struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
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struct acp_dsp_stream *dtrace_stream;
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struct pci_dev *smn_dev;
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};
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void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
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void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
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int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
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int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
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unsigned int dest_addr, int dsp_data_size);
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int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
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unsigned int start_addr, unsigned int dest_addr,
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unsigned int image_length);
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/* ACP device probe/remove */
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int amd_sof_acp_probe(struct snd_sof_dev *sdev);
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int amd_sof_acp_remove(struct snd_sof_dev *sdev);
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/* DSP Loader callbacks */
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int acp_sof_dsp_run(struct snd_sof_dev *sdev);
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int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
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int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
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/* Block IO callbacks */
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int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
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u32 offset, void *src, size_t size);
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int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
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u32 offset, void *dest, size_t size);
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/* IPC callbacks */
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irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
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int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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void *p, size_t sz);
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int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg);
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int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
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int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
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void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
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void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
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/* ACP - DSP stream callbacks */
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int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
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int acp_dsp_stream_init(struct snd_sof_dev *sdev);
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struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
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int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
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/*
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* DSP PCM Operations.
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*/
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int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
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int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
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int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_sof_platform_stream_params *platform_params);
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extern struct snd_sof_dsp_ops sof_acp_common_ops;
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extern struct snd_sof_dsp_ops sof_renoir_ops;
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int sof_renoir_ops_init(struct snd_sof_dev *sdev);
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extern struct snd_sof_dsp_ops sof_rembrandt_ops;
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int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
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int acp_dai_probe(struct snd_soc_dai *dai);
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struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
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/* Machine configuration */
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int snd_amd_acp_find_config(struct pci_dev *pci);
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/* Trace */
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int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
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struct sof_ipc_dma_trace_params_ext *dtrace_params);
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int acp_sof_trace_release(struct snd_sof_dev *sdev);
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/* PM Callbacks */
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int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
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int amd_sof_acp_resume(struct snd_sof_dev *sdev);
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static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
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{
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const struct sof_dev_desc *desc = pdata->desc;
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return desc->chip_info;
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}
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#endif
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