217 lines
6.4 KiB
C
217 lines
6.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2021 Advanced Micro Devices, Inc.
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//
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// Authors: Balakishore Pati <Balakishore.pati@amd.com>
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// Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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/* ACP-specific SOF IPC code */
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#include <linux/module.h>
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#include "../ops.h"
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#include "acp.h"
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#include "acp-dsp-offset.h"
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void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
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{
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memcpy_to_scratch(sdev, offset, message, bytes);
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}
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EXPORT_SYMBOL_NS(acp_mailbox_write, SND_SOC_SOF_AMD_COMMON);
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void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
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{
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memcpy_from_scratch(sdev, offset, message, bytes);
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}
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EXPORT_SYMBOL_NS(acp_mailbox_read, SND_SOC_SOF_AMD_COMMON);
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static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata)
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{
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struct snd_sof_dev *sdev = adata->dev;
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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u32 swintr_trigger;
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swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->dsp_intr_base +
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DSP_SW_INTR_TRIG_OFFSET);
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swintr_trigger |= 0x01;
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_TRIG_OFFSET,
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swintr_trigger);
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}
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static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev)
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{
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unsigned int host_msg = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_host_msg_write);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1);
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}
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static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev)
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{
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unsigned int dsp_msg = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0);
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}
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static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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unsigned int dsp_ack = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0);
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}
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int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct acp_dev_data *adata = sdev->pdata->hw_pdata;
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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unsigned int offset = sdev->host_box.offset;
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unsigned int count = ACP_HW_SEM_RETRY_COUNT;
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while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
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/* Wait until acquired HW Semaphore Lock or timeout*/
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count--;
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if (!count) {
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dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
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return -EINVAL;
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}
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}
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acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
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acp_ipc_host_msg_set(sdev);
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/* Trigger host to dsp interrupt for the msg */
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acpbus_trigger_host_to_dsp_swintr(adata);
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/* Unlock or Release HW Semaphore */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, SND_SOC_SOF_AMD_COMMON);
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static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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struct sof_ipc_cmd_hdr *hdr;
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unsigned int offset = sdev->host_box.offset;
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int ret = 0;
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/*
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* Sometimes, there is unexpected reply ipc arriving. The reply
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* ipc belongs to none of the ipcs sent from driver.
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* In this case, the driver must ignore the ipc.
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*/
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
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return;
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}
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hdr = msg->msg_data;
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if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
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hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
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/*
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* memory windows are powered off before sending IPC reply,
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* so we can't read the mailbox for CTX_SAVE and PM_GATE
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* replies.
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*/
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reply.error = 0;
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reply.hdr.cmd = SOF_IPC_GLB_REPLY;
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reply.hdr.size = sizeof(reply);
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memcpy(msg->reply_data, &reply, sizeof(reply));
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goto out;
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}
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/* get IPC reply from DSP in the mailbox */
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acp_mailbox_read(sdev, offset, &reply, sizeof(reply));
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if (reply.error < 0) {
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memcpy(msg->reply_data, &reply, sizeof(reply));
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ret = reply.error;
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} else {
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/* reply correct size ? */
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if (reply.hdr.size != msg->reply_size &&
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!(reply.hdr.cmd & SOF_IPC_GLB_PROBE)) {
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dev_err(sdev->dev, "reply expected %zu got %u bytes\n",
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msg->reply_size, reply.hdr.size);
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ret = -EINVAL;
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}
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/* read the message */
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if (msg->reply_size > 0)
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acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size);
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}
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out:
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msg->reply_error = ret;
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}
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irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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unsigned int dsp_msg_write = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
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unsigned int dsp_ack_write = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
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bool ipc_irq = false;
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int dsp_msg, dsp_ack;
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if (sdev->first_boot && sdev->fw_state != SOF_FW_BOOT_COMPLETE) {
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snd_sof_ipc_msgs_rx(sdev);
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acp_dsp_ipc_host_done(sdev);
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return IRQ_HANDLED;
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}
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dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
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if (dsp_msg) {
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snd_sof_ipc_msgs_rx(sdev);
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acp_dsp_ipc_host_done(sdev);
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ipc_irq = true;
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}
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dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
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if (dsp_ack) {
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spin_lock_irq(&sdev->ipc_lock);
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/* handle immediate reply from DSP core */
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acp_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, 0);
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/* set the done bit */
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acp_dsp_ipc_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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ipc_irq = true;
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}
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if (!ipc_irq)
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dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_irq_thread, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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void *p, size_t sz)
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{
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unsigned int offset = sdev->dsp_box.offset;
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if (!substream || !sdev->stream_box.size)
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acp_mailbox_read(sdev, offset, p, sz);
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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return desc->sram_pte_offset;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_get_mailbox_offset, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_get_window_offset, SND_SOC_SOF_AMD_COMMON);
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MODULE_DESCRIPTION("AMD ACP sof-ipc driver");
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