299 lines
8.0 KiB
C
299 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mt2701-afe-clock-ctrl.c -- Mediatek 2701 afe clock ctrl
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*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Garlic Tseng <garlic.tseng@mediatek.com>
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* Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include "mt2701-afe-common.h"
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#include "mt2701-afe-clock-ctrl.h"
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static const char *const base_clks[] = {
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[MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
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[MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
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[MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
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[MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
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[MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
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[MT2701_AUDSYS_AFE] = "audio_afe_pd",
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[MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
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[MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
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[MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
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};
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int mt2701_init_clock(struct mtk_base_afe *afe)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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int i;
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for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
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afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
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if (IS_ERR(afe_priv->base_ck[i])) {
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dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
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return PTR_ERR(afe_priv->base_ck[i]);
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}
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}
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/* Get I2S related clocks */
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for (i = 0; i < afe_priv->soc->i2s_num; i++) {
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struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
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struct clk *i2s_ck;
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char name[13];
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snprintf(name, sizeof(name), "i2s%d_src_sel", i);
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i2s_path->sel_ck = devm_clk_get(afe->dev, name);
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if (IS_ERR(i2s_path->sel_ck)) {
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dev_err(afe->dev, "failed to get %s\n", name);
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return PTR_ERR(i2s_path->sel_ck);
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}
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snprintf(name, sizeof(name), "i2s%d_src_div", i);
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i2s_path->div_ck = devm_clk_get(afe->dev, name);
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if (IS_ERR(i2s_path->div_ck)) {
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dev_err(afe->dev, "failed to get %s\n", name);
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return PTR_ERR(i2s_path->div_ck);
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}
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snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
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i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
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if (IS_ERR(i2s_path->mclk_ck)) {
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dev_err(afe->dev, "failed to get %s\n", name);
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return PTR_ERR(i2s_path->mclk_ck);
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}
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snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
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i2s_ck = devm_clk_get(afe->dev, name);
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if (IS_ERR(i2s_ck)) {
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dev_err(afe->dev, "failed to get %s\n", name);
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return PTR_ERR(i2s_ck);
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}
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i2s_path->hop_ck[SNDRV_PCM_STREAM_PLAYBACK] = i2s_ck;
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snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
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i2s_ck = devm_clk_get(afe->dev, name);
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if (IS_ERR(i2s_ck)) {
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dev_err(afe->dev, "failed to get %s\n", name);
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return PTR_ERR(i2s_ck);
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}
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i2s_path->hop_ck[SNDRV_PCM_STREAM_CAPTURE] = i2s_ck;
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snprintf(name, sizeof(name), "asrc%d_out_ck", i);
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i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
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if (IS_ERR(i2s_path->asrco_ck)) {
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dev_err(afe->dev, "failed to get %s\n", name);
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return PTR_ERR(i2s_path->asrco_ck);
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}
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}
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/* Some platforms may support BT path */
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afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
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if (IS_ERR(afe_priv->mrgif_ck)) {
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if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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afe_priv->mrgif_ck = NULL;
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}
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return 0;
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}
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int mt2701_afe_enable_i2s(struct mtk_base_afe *afe,
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struct mt2701_i2s_path *i2s_path,
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int dir)
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{
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int ret;
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ret = clk_prepare_enable(i2s_path->asrco_ck);
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if (ret) {
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dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
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if (ret) {
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dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
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goto err_hop_ck;
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}
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return 0;
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err_hop_ck:
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clk_disable_unprepare(i2s_path->asrco_ck);
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return ret;
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}
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void mt2701_afe_disable_i2s(struct mtk_base_afe *afe,
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struct mt2701_i2s_path *i2s_path,
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int dir)
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{
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clk_disable_unprepare(i2s_path->hop_ck[dir]);
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clk_disable_unprepare(i2s_path->asrco_ck);
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}
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int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
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return clk_prepare_enable(i2s_path->mclk_ck);
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}
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void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
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clk_disable_unprepare(i2s_path->mclk_ck);
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}
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int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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return clk_prepare_enable(afe_priv->mrgif_ck);
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}
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void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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clk_disable_unprepare(afe_priv->mrgif_ck);
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}
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static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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int ret;
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/* Enable infra clock gate */
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
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if (ret)
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return ret;
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/* Enable top a1sys clock gate */
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
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if (ret)
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goto err_a1sys;
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/* Enable top a2sys clock gate */
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
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if (ret)
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goto err_a2sys;
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/* Internal clock gates */
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
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if (ret)
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goto err_afe;
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
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if (ret)
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goto err_audio_a1sys;
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
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if (ret)
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goto err_audio_a2sys;
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ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
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if (ret)
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goto err_afe_conn;
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return 0;
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err_afe_conn:
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
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err_audio_a2sys:
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
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err_audio_a1sys:
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
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err_afe:
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clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
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err_a2sys:
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clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
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err_a1sys:
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clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
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return ret;
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}
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static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
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clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
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clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
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clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
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clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
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}
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int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
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{
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int ret;
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/* Enable audio system */
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ret = mt2701_afe_enable_audsys(afe);
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if (ret) {
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dev_err(afe->dev, "failed to enable audio system %d\n", ret);
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return ret;
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}
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regmap_update_bits(afe->regmap, ASYS_TOP_CON,
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ASYS_TOP_CON_ASYS_TIMING_ON,
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ASYS_TOP_CON_ASYS_TIMING_ON);
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regmap_update_bits(afe->regmap, AFE_DAC_CON0,
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AFE_DAC_CON0_AFE_ON,
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AFE_DAC_CON0_AFE_ON);
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/* Configure ASRC */
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regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
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regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
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return 0;
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}
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int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
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{
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regmap_update_bits(afe->regmap, ASYS_TOP_CON,
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ASYS_TOP_CON_ASYS_TIMING_ON, 0);
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regmap_update_bits(afe->regmap, AFE_DAC_CON0,
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AFE_DAC_CON0_AFE_ON, 0);
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mt2701_afe_disable_audsys(afe);
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return 0;
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}
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int mt2701_mclk_configuration(struct mtk_base_afe *afe, int id)
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{
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struct mt2701_afe_private *priv = afe->platform_priv;
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struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
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int ret = -EINVAL;
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/* Set mclk source */
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if (!(MT2701_PLL_DOMAIN_0_RATE % i2s_path->mclk_rate))
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ret = clk_set_parent(i2s_path->sel_ck,
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priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
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else if (!(MT2701_PLL_DOMAIN_1_RATE % i2s_path->mclk_rate))
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ret = clk_set_parent(i2s_path->sel_ck,
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priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
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if (ret) {
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dev_err(afe->dev, "failed to set mclk source\n");
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return ret;
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}
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/* Set mclk divider */
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ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate);
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if (ret) {
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dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
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return ret;
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}
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return 0;
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}
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