902 lines
25 KiB
C
902 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* es8328.c -- ES8328 ALSA SoC Audio driver
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*
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* Copyright 2014 Sutajio Ko-Usagi PTE LTD
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*
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* Author: Sean Cross <xobs@kosagi.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/regulator/consumer.h>
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#include <sound/core.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/tlv.h>
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#include "es8328.h"
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static const unsigned int rates_12288[] = {
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8000, 12000, 16000, 24000, 32000, 48000, 96000,
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};
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static const int ratios_12288[] = {
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10, 7, 6, 4, 3, 2, 0,
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};
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static const struct snd_pcm_hw_constraint_list constraints_12288 = {
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.count = ARRAY_SIZE(rates_12288),
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.list = rates_12288,
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};
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static unsigned int ratios_12000[] = {
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8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
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48000, 88235, 96000,
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};
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static struct snd_pcm_hw_constraint_list constraints_12000 = {
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.count = ARRAY_SIZE(ratios_12000),
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.list = ratios_12000,
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};
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static const unsigned int rates_11289[] = {
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8018, 11025, 22050, 44100, 88200,
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};
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static const int ratios_11289[] = {
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9, 7, 4, 2, 0,
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};
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static const struct snd_pcm_hw_constraint_list constraints_11289 = {
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.count = ARRAY_SIZE(rates_11289),
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.list = rates_11289,
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};
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/* regulator supplies for sgtl5000, VDDD is an optional external supply */
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enum sgtl5000_regulator_supplies {
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DVDD,
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AVDD,
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PVDD,
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HPVDD,
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ES8328_SUPPLY_NUM
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};
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/* vddd is optional supply */
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static const char * const supply_names[ES8328_SUPPLY_NUM] = {
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"DVDD",
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"AVDD",
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"PVDD",
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"HPVDD",
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};
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#define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
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SNDRV_PCM_RATE_96000 | \
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SNDRV_PCM_RATE_88200 | \
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SNDRV_PCM_RATE_8000_48000)
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#define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S18_3LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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struct es8328_priv {
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struct regmap *regmap;
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struct clk *clk;
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int playback_fs;
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bool deemph;
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int mclkdiv2;
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const struct snd_pcm_hw_constraint_list *sysclk_constraints;
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const int *mclk_ratios;
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bool provider;
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struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
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};
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/*
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* ES8328 Controls
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*/
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static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
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"L + R Invert"};
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static SOC_ENUM_SINGLE_DECL(adcpol,
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ES8328_ADCCONTROL6, 6, adcpol_txt);
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static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
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static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
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static const struct {
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int rate;
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unsigned int val;
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} deemph_settings[] = {
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{ 0, ES8328_DACCONTROL6_DEEMPH_OFF },
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{ 32000, ES8328_DACCONTROL6_DEEMPH_32k },
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{ 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
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{ 48000, ES8328_DACCONTROL6_DEEMPH_48k },
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};
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static int es8328_set_deemph(struct snd_soc_component *component)
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{
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struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
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int val, i, best;
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/*
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* If we're using deemphasis select the nearest available sample
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* rate.
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*/
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if (es8328->deemph) {
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best = 0;
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for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
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if (abs(deemph_settings[i].rate - es8328->playback_fs) <
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abs(deemph_settings[best].rate - es8328->playback_fs))
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best = i;
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}
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val = deemph_settings[best].val;
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} else {
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val = ES8328_DACCONTROL6_DEEMPH_OFF;
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}
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dev_dbg(component->dev, "Set deemphasis %d\n", val);
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return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
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ES8328_DACCONTROL6_DEEMPH_MASK, val);
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}
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static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
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ucontrol->value.integer.value[0] = es8328->deemph;
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return 0;
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}
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static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
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unsigned int deemph = ucontrol->value.integer.value[0];
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int ret;
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if (deemph > 1)
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return -EINVAL;
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if (es8328->deemph == deemph)
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return 0;
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ret = es8328_set_deemph(component);
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if (ret < 0)
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return ret;
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es8328->deemph = deemph;
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return 1;
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}
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static const struct snd_kcontrol_new es8328_snd_controls[] = {
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SOC_DOUBLE_R_TLV("Capture Digital Volume",
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ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
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0, 0xc0, 1, dac_adc_tlv),
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SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
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SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
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es8328_get_deemph, es8328_put_deemph),
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SOC_ENUM("Capture Polarity", adcpol),
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SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
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ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
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SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
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ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
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SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
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ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
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SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
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ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
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SOC_DOUBLE_R_TLV("PCM Volume",
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ES8328_LDACVOL, ES8328_RDACVOL,
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0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
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SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
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ES8328_LOUT1VOL, ES8328_ROUT1VOL,
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0, ES8328_OUT1VOL_MAX, 0, play_tlv),
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SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
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ES8328_LOUT2VOL, ES8328_ROUT2VOL,
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0, ES8328_OUT2VOL_MAX, 0, play_tlv),
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SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
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4, 0, 8, 0, mic_tlv),
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};
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/*
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* DAPM Controls
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*/
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static const char * const es8328_line_texts[] = {
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"Line 1", "Line 2", "PGA", "Differential"};
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static const struct soc_enum es8328_lline_enum =
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SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
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ARRAY_SIZE(es8328_line_texts),
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es8328_line_texts);
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static const struct snd_kcontrol_new es8328_left_line_controls =
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SOC_DAPM_ENUM("Route", es8328_lline_enum);
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static const struct soc_enum es8328_rline_enum =
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SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
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ARRAY_SIZE(es8328_line_texts),
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es8328_line_texts);
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static const struct snd_kcontrol_new es8328_right_line_controls =
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SOC_DAPM_ENUM("Route", es8328_rline_enum);
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/* Left Mixer */
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static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
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SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
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SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
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SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
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SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
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};
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/* Right Mixer */
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static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
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SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
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SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
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SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
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SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
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};
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static const char * const es8328_pga_sel[] = {
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"Line 1", "Line 2", "Line 3", "Differential"};
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/* Left PGA Mux */
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static const struct soc_enum es8328_lpga_enum =
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SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
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ARRAY_SIZE(es8328_pga_sel),
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es8328_pga_sel);
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static const struct snd_kcontrol_new es8328_left_pga_controls =
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SOC_DAPM_ENUM("Route", es8328_lpga_enum);
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/* Right PGA Mux */
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static const struct soc_enum es8328_rpga_enum =
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SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
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ARRAY_SIZE(es8328_pga_sel),
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es8328_pga_sel);
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static const struct snd_kcontrol_new es8328_right_pga_controls =
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SOC_DAPM_ENUM("Route", es8328_rpga_enum);
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/* Differential Mux */
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static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
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static SOC_ENUM_SINGLE_DECL(diffmux,
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ES8328_ADCCONTROL3, 7, es8328_diff_sel);
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static const struct snd_kcontrol_new es8328_diffmux_controls =
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SOC_DAPM_ENUM("Route", diffmux);
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/* Mono ADC Mux */
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static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
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"Mono (Right)", "Digital Mono"};
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static SOC_ENUM_SINGLE_DECL(monomux,
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ES8328_ADCCONTROL3, 3, es8328_mono_mux);
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static const struct snd_kcontrol_new es8328_monomux_controls =
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SOC_DAPM_ENUM("Route", monomux);
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static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
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SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
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&es8328_diffmux_controls),
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SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
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&es8328_monomux_controls),
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SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
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&es8328_monomux_controls),
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SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
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ES8328_ADCPOWER_AINL_OFF, 1,
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&es8328_left_pga_controls),
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SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
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ES8328_ADCPOWER_AINR_OFF, 1,
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&es8328_right_pga_controls),
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SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
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&es8328_left_line_controls),
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SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
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&es8328_right_line_controls),
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SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
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ES8328_ADCPOWER_ADCR_OFF, 1),
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SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
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ES8328_ADCPOWER_ADCL_OFF, 1),
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SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
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ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
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ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
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SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
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ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
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SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
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ES8328_DACPOWER_RDAC_OFF, 1),
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SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
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ES8328_DACPOWER_LDAC_OFF, 1),
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SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
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&es8328_left_mixer_controls[0],
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ARRAY_SIZE(es8328_left_mixer_controls)),
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SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
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&es8328_right_mixer_controls[0],
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ARRAY_SIZE(es8328_right_mixer_controls)),
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SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
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ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
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SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
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ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
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SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
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ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
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SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
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ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
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SND_SOC_DAPM_OUTPUT("LOUT1"),
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SND_SOC_DAPM_OUTPUT("ROUT1"),
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SND_SOC_DAPM_OUTPUT("LOUT2"),
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SND_SOC_DAPM_OUTPUT("ROUT2"),
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SND_SOC_DAPM_INPUT("LINPUT1"),
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SND_SOC_DAPM_INPUT("LINPUT2"),
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SND_SOC_DAPM_INPUT("RINPUT1"),
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SND_SOC_DAPM_INPUT("RINPUT2"),
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};
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static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
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{ "Left Line Mux", "Line 1", "LINPUT1" },
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{ "Left Line Mux", "Line 2", "LINPUT2" },
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{ "Left Line Mux", "PGA", "Left PGA Mux" },
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{ "Left Line Mux", "Differential", "Differential Mux" },
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{ "Right Line Mux", "Line 1", "RINPUT1" },
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{ "Right Line Mux", "Line 2", "RINPUT2" },
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{ "Right Line Mux", "PGA", "Right PGA Mux" },
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{ "Right Line Mux", "Differential", "Differential Mux" },
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{ "Left PGA Mux", "Line 1", "LINPUT1" },
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{ "Left PGA Mux", "Line 2", "LINPUT2" },
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{ "Left PGA Mux", "Differential", "Differential Mux" },
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{ "Right PGA Mux", "Line 1", "RINPUT1" },
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{ "Right PGA Mux", "Line 2", "RINPUT2" },
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{ "Right PGA Mux", "Differential", "Differential Mux" },
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{ "Differential Mux", "Line 1", "LINPUT1" },
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{ "Differential Mux", "Line 1", "RINPUT1" },
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{ "Differential Mux", "Line 2", "LINPUT2" },
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{ "Differential Mux", "Line 2", "RINPUT2" },
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{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
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{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
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{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
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{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
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{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
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{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
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{ "Left ADC", NULL, "Left ADC Mux" },
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{ "Right ADC", NULL, "Right ADC Mux" },
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{ "ADC DIG", NULL, "ADC STM" },
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{ "ADC DIG", NULL, "ADC Vref" },
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{ "ADC DIG", NULL, "ADC DLL" },
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{ "Left ADC", NULL, "ADC DIG" },
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{ "Right ADC", NULL, "ADC DIG" },
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|
|
{ "Mic Bias", NULL, "Mic Bias Gen" },
|
|
|
|
{ "Left Line Mux", "Line 1", "LINPUT1" },
|
|
{ "Left Line Mux", "Line 2", "LINPUT2" },
|
|
{ "Left Line Mux", "PGA", "Left PGA Mux" },
|
|
{ "Left Line Mux", "Differential", "Differential Mux" },
|
|
|
|
{ "Right Line Mux", "Line 1", "RINPUT1" },
|
|
{ "Right Line Mux", "Line 2", "RINPUT2" },
|
|
{ "Right Line Mux", "PGA", "Right PGA Mux" },
|
|
{ "Right Line Mux", "Differential", "Differential Mux" },
|
|
|
|
{ "Left Out 1", NULL, "Left DAC" },
|
|
{ "Right Out 1", NULL, "Right DAC" },
|
|
{ "Left Out 2", NULL, "Left DAC" },
|
|
{ "Right Out 2", NULL, "Right DAC" },
|
|
|
|
{ "Left Mixer", "Playback Switch", "Left DAC" },
|
|
{ "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
|
|
{ "Left Mixer", "Right Playback Switch", "Right DAC" },
|
|
{ "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
|
|
|
|
{ "Right Mixer", "Left Playback Switch", "Left DAC" },
|
|
{ "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
|
|
{ "Right Mixer", "Playback Switch", "Right DAC" },
|
|
{ "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
|
|
|
|
{ "DAC DIG", NULL, "DAC STM" },
|
|
{ "DAC DIG", NULL, "DAC Vref" },
|
|
{ "DAC DIG", NULL, "DAC DLL" },
|
|
|
|
{ "Left DAC", NULL, "DAC DIG" },
|
|
{ "Right DAC", NULL, "DAC DIG" },
|
|
|
|
{ "Left Out 1", NULL, "Left Mixer" },
|
|
{ "LOUT1", NULL, "Left Out 1" },
|
|
{ "Right Out 1", NULL, "Right Mixer" },
|
|
{ "ROUT1", NULL, "Right Out 1" },
|
|
|
|
{ "Left Out 2", NULL, "Left Mixer" },
|
|
{ "LOUT2", NULL, "Left Out 2" },
|
|
{ "Right Out 2", NULL, "Right Mixer" },
|
|
{ "ROUT2", NULL, "Right Out 2" },
|
|
};
|
|
|
|
static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction)
|
|
{
|
|
return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
|
|
ES8328_DACCONTROL3_DACMUTE,
|
|
mute ? ES8328_DACCONTROL3_DACMUTE : 0);
|
|
}
|
|
|
|
static int es8328_startup(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_component *component = dai->component;
|
|
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
|
|
|
|
if (es8328->provider && es8328->sysclk_constraints)
|
|
snd_pcm_hw_constraint_list(substream->runtime, 0,
|
|
SNDRV_PCM_HW_PARAM_RATE,
|
|
es8328->sysclk_constraints);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int es8328_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_component *component = dai->component;
|
|
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
|
|
int i;
|
|
int reg;
|
|
int wl;
|
|
int ratio;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
reg = ES8328_DACCONTROL2;
|
|
else
|
|
reg = ES8328_ADCCONTROL5;
|
|
|
|
if (es8328->provider) {
|
|
if (!es8328->sysclk_constraints) {
|
|
dev_err(component->dev, "No MCLK configured\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < es8328->sysclk_constraints->count; i++)
|
|
if (es8328->sysclk_constraints->list[i] ==
|
|
params_rate(params))
|
|
break;
|
|
|
|
if (i == es8328->sysclk_constraints->count) {
|
|
dev_err(component->dev,
|
|
"LRCLK %d unsupported with current clock\n",
|
|
params_rate(params));
|
|
return -EINVAL;
|
|
}
|
|
ratio = es8328->mclk_ratios[i];
|
|
} else {
|
|
ratio = 0;
|
|
es8328->mclkdiv2 = 0;
|
|
}
|
|
|
|
snd_soc_component_update_bits(component, ES8328_MASTERMODE,
|
|
ES8328_MASTERMODE_MCLKDIV2,
|
|
es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
|
|
|
|
switch (params_width(params)) {
|
|
case 16:
|
|
wl = 3;
|
|
break;
|
|
case 18:
|
|
wl = 2;
|
|
break;
|
|
case 20:
|
|
wl = 1;
|
|
break;
|
|
case 24:
|
|
wl = 0;
|
|
break;
|
|
case 32:
|
|
wl = 4;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
|
|
ES8328_DACCONTROL1_DACWL_MASK,
|
|
wl << ES8328_DACCONTROL1_DACWL_SHIFT);
|
|
|
|
es8328->playback_fs = params_rate(params);
|
|
es8328_set_deemph(component);
|
|
} else
|
|
snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
|
|
ES8328_ADCCONTROL4_ADCWL_MASK,
|
|
wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
|
|
|
|
return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
|
|
}
|
|
|
|
static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
|
|
int clk_id, unsigned int freq, int dir)
|
|
{
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
|
|
int mclkdiv2 = 0;
|
|
|
|
switch (freq) {
|
|
case 0:
|
|
es8328->sysclk_constraints = NULL;
|
|
es8328->mclk_ratios = NULL;
|
|
break;
|
|
case 22579200:
|
|
mclkdiv2 = 1;
|
|
fallthrough;
|
|
case 11289600:
|
|
es8328->sysclk_constraints = &constraints_11289;
|
|
es8328->mclk_ratios = ratios_11289;
|
|
break;
|
|
case 24576000:
|
|
mclkdiv2 = 1;
|
|
fallthrough;
|
|
case 12288000:
|
|
es8328->sysclk_constraints = &constraints_12288;
|
|
es8328->mclk_ratios = ratios_12288;
|
|
break;
|
|
|
|
case 24000000:
|
|
mclkdiv2 = 1;
|
|
fallthrough;
|
|
case 12000000:
|
|
es8328->sysclk_constraints = &constraints_12000;
|
|
es8328->mclk_ratios = ratios_12000;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
es8328->mclkdiv2 = mclkdiv2;
|
|
return 0;
|
|
}
|
|
|
|
static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
|
|
unsigned int fmt)
|
|
{
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
|
|
u8 dac_mode = 0;
|
|
u8 adc_mode = 0;
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
|
|
case SND_SOC_DAIFMT_CBP_CFP:
|
|
/* Master serial port mode, with BCLK generated automatically */
|
|
snd_soc_component_update_bits(component, ES8328_MASTERMODE,
|
|
ES8328_MASTERMODE_MSC,
|
|
ES8328_MASTERMODE_MSC);
|
|
es8328->provider = true;
|
|
break;
|
|
case SND_SOC_DAIFMT_CBC_CFC:
|
|
/* Slave serial port mode */
|
|
snd_soc_component_update_bits(component, ES8328_MASTERMODE,
|
|
ES8328_MASTERMODE_MSC, 0);
|
|
es8328->provider = false;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* interface format */
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
case SND_SOC_DAIFMT_I2S:
|
|
dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
|
|
adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
|
|
break;
|
|
case SND_SOC_DAIFMT_RIGHT_J:
|
|
dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
|
|
adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
|
|
break;
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
|
|
adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* clock inversion */
|
|
if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
|
|
return -EINVAL;
|
|
|
|
snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
|
|
ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
|
|
snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
|
|
ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int es8328_set_bias_level(struct snd_soc_component *component,
|
|
enum snd_soc_bias_level level)
|
|
{
|
|
switch (level) {
|
|
case SND_SOC_BIAS_ON:
|
|
break;
|
|
|
|
case SND_SOC_BIAS_PREPARE:
|
|
/* VREF, VMID=2x50k, digital enabled */
|
|
snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
|
|
snd_soc_component_update_bits(component, ES8328_CONTROL1,
|
|
ES8328_CONTROL1_VMIDSEL_MASK |
|
|
ES8328_CONTROL1_ENREF,
|
|
ES8328_CONTROL1_VMIDSEL_50k |
|
|
ES8328_CONTROL1_ENREF);
|
|
break;
|
|
|
|
case SND_SOC_BIAS_STANDBY:
|
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
|
|
snd_soc_component_update_bits(component, ES8328_CONTROL1,
|
|
ES8328_CONTROL1_VMIDSEL_MASK |
|
|
ES8328_CONTROL1_ENREF,
|
|
ES8328_CONTROL1_VMIDSEL_5k |
|
|
ES8328_CONTROL1_ENREF);
|
|
|
|
/* Charge caps */
|
|
msleep(100);
|
|
}
|
|
|
|
snd_soc_component_write(component, ES8328_CONTROL2,
|
|
ES8328_CONTROL2_OVERCURRENT_ON |
|
|
ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
|
|
|
|
/* VREF, VMID=2*500k, digital stopped */
|
|
snd_soc_component_update_bits(component, ES8328_CONTROL1,
|
|
ES8328_CONTROL1_VMIDSEL_MASK |
|
|
ES8328_CONTROL1_ENREF,
|
|
ES8328_CONTROL1_VMIDSEL_500k |
|
|
ES8328_CONTROL1_ENREF);
|
|
break;
|
|
|
|
case SND_SOC_BIAS_OFF:
|
|
snd_soc_component_update_bits(component, ES8328_CONTROL1,
|
|
ES8328_CONTROL1_VMIDSEL_MASK |
|
|
ES8328_CONTROL1_ENREF,
|
|
0);
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops es8328_dai_ops = {
|
|
.startup = es8328_startup,
|
|
.hw_params = es8328_hw_params,
|
|
.mute_stream = es8328_mute,
|
|
.set_sysclk = es8328_set_sysclk,
|
|
.set_fmt = es8328_set_dai_fmt,
|
|
.no_capture_mute = 1,
|
|
};
|
|
|
|
static struct snd_soc_dai_driver es8328_dai = {
|
|
.name = "es8328-hifi-analog",
|
|
.playback = {
|
|
.stream_name = "Playback",
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = ES8328_RATES,
|
|
.formats = ES8328_FORMATS,
|
|
},
|
|
.capture = {
|
|
.stream_name = "Capture",
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = ES8328_RATES,
|
|
.formats = ES8328_FORMATS,
|
|
},
|
|
.ops = &es8328_dai_ops,
|
|
.symmetric_rate = 1,
|
|
};
|
|
|
|
static int es8328_suspend(struct snd_soc_component *component)
|
|
{
|
|
struct es8328_priv *es8328;
|
|
int ret;
|
|
|
|
es8328 = snd_soc_component_get_drvdata(component);
|
|
|
|
clk_disable_unprepare(es8328->clk);
|
|
|
|
ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
|
|
es8328->supplies);
|
|
if (ret) {
|
|
dev_err(component->dev, "unable to disable regulators\n");
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int es8328_resume(struct snd_soc_component *component)
|
|
{
|
|
struct regmap *regmap = dev_get_regmap(component->dev, NULL);
|
|
struct es8328_priv *es8328;
|
|
int ret;
|
|
|
|
es8328 = snd_soc_component_get_drvdata(component);
|
|
|
|
ret = clk_prepare_enable(es8328->clk);
|
|
if (ret) {
|
|
dev_err(component->dev, "unable to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
|
|
es8328->supplies);
|
|
if (ret) {
|
|
dev_err(component->dev, "unable to enable regulators\n");
|
|
return ret;
|
|
}
|
|
|
|
regcache_mark_dirty(regmap);
|
|
ret = regcache_sync(regmap);
|
|
if (ret) {
|
|
dev_err(component->dev, "unable to sync regcache\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int es8328_component_probe(struct snd_soc_component *component)
|
|
{
|
|
struct es8328_priv *es8328;
|
|
int ret;
|
|
|
|
es8328 = snd_soc_component_get_drvdata(component);
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
|
|
es8328->supplies);
|
|
if (ret) {
|
|
dev_err(component->dev, "unable to enable regulators\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Setup clocks */
|
|
es8328->clk = devm_clk_get(component->dev, NULL);
|
|
if (IS_ERR(es8328->clk)) {
|
|
dev_err(component->dev, "codec clock missing or invalid\n");
|
|
ret = PTR_ERR(es8328->clk);
|
|
goto clk_fail;
|
|
}
|
|
|
|
ret = clk_prepare_enable(es8328->clk);
|
|
if (ret) {
|
|
dev_err(component->dev, "unable to prepare codec clk\n");
|
|
goto clk_fail;
|
|
}
|
|
|
|
return 0;
|
|
|
|
clk_fail:
|
|
regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
|
|
es8328->supplies);
|
|
return ret;
|
|
}
|
|
|
|
static void es8328_remove(struct snd_soc_component *component)
|
|
{
|
|
struct es8328_priv *es8328;
|
|
|
|
es8328 = snd_soc_component_get_drvdata(component);
|
|
|
|
clk_disable_unprepare(es8328->clk);
|
|
|
|
regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
|
|
es8328->supplies);
|
|
}
|
|
|
|
const struct regmap_config es8328_regmap_config = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
.max_register = ES8328_REG_MAX,
|
|
.cache_type = REGCACHE_RBTREE,
|
|
.use_single_read = true,
|
|
.use_single_write = true,
|
|
};
|
|
EXPORT_SYMBOL_GPL(es8328_regmap_config);
|
|
|
|
static const struct snd_soc_component_driver es8328_component_driver = {
|
|
.probe = es8328_component_probe,
|
|
.remove = es8328_remove,
|
|
.suspend = es8328_suspend,
|
|
.resume = es8328_resume,
|
|
.set_bias_level = es8328_set_bias_level,
|
|
.controls = es8328_snd_controls,
|
|
.num_controls = ARRAY_SIZE(es8328_snd_controls),
|
|
.dapm_widgets = es8328_dapm_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
|
|
.dapm_routes = es8328_dapm_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes),
|
|
.suspend_bias_off = 1,
|
|
.idle_bias_on = 1,
|
|
.use_pmdown_time = 1,
|
|
.endianness = 1,
|
|
};
|
|
|
|
int es8328_probe(struct device *dev, struct regmap *regmap)
|
|
{
|
|
struct es8328_priv *es8328;
|
|
int ret;
|
|
int i;
|
|
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
|
|
if (es8328 == NULL)
|
|
return -ENOMEM;
|
|
|
|
es8328->regmap = regmap;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
|
|
es8328->supplies[i].supply = supply_names[i];
|
|
|
|
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
|
|
es8328->supplies);
|
|
if (ret) {
|
|
dev_err(dev, "unable to get regulators\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_set_drvdata(dev, es8328);
|
|
|
|
return devm_snd_soc_register_component(dev,
|
|
&es8328_component_driver, &es8328_dai, 1);
|
|
}
|
|
EXPORT_SYMBOL_GPL(es8328_probe);
|
|
|
|
MODULE_DESCRIPTION("ASoC ES8328 driver");
|
|
MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
|
|
MODULE_LICENSE("GPL");
|