631 lines
20 KiB
C
631 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_gpio.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/version.h>
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#include <linux/workqueue.h>
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#include <linux/syscalls.h>
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#include <sound/control.h>
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#include <linux/uaccess.h>
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#include <linux/syscalls.h>
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#include "aw883xx.h"
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#include "aw_bin_parse.h"
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#include "aw_pid_2049_reg.h"
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#include "aw_log.h"
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#define AW_FW_CHECK_PART (10)
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static int aw883xx_dev_i2c_writes(struct aw_device *aw_dev,
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uint8_t reg_addr, uint8_t *buf, uint16_t len)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_i2c_writes(aw883xx, reg_addr, buf, len);
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}
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static int aw883xx_dev_i2c_write(struct aw_device *aw_dev,
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uint8_t reg_addr, uint16_t reg_data)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_i2c_write(aw883xx, reg_addr, reg_data);
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}
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static int aw883xx_dev_i2c_read(struct aw_device *aw_dev,
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uint8_t reg_addr, uint16_t *reg_data)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_i2c_read(aw883xx, reg_addr, reg_data);
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}
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static int aw883xx_dev_reg_read(struct aw_device *aw_dev,
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uint8_t reg_addr, uint16_t *reg_data)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_reg_read(aw883xx, reg_addr, reg_data);
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}
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static int aw883xx_dev_reg_write(struct aw_device *aw_dev,
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uint8_t reg_addr, uint16_t reg_data)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_reg_write(aw883xx, reg_addr, reg_data);
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}
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static int aw883xx_dev_reg_write_bits(struct aw_device *aw_dev,
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uint8_t reg_addr, uint16_t mask, uint16_t reg_data)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_reg_write_bits(aw883xx, reg_addr, mask, reg_data);
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}
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static int aw883xx_dev_dsp_write(struct aw_device *aw_dev,
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uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_dsp_write(aw883xx, dsp_addr, dsp_data, data_type);
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}
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static int aw883xx_dev_dsp_read(struct aw_device *aw_dev,
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uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_dsp_read(aw883xx, dsp_addr, dsp_data, data_type);
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}
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/******************************************************
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*
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* aw883xx i2c write/read
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*
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******************************************************/
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/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB real_value = value * 8 : 0.125db --> 1*/
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static unsigned int aw_pid_2049_reg_val_to_db(unsigned int value)
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{
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return (((value >> AW_PID_2049_VOL_6DB_START) * AW_PID_2049_VOLUME_STEP_DB) +
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((value & 0x3f) % AW_PID_2049_VOLUME_STEP_DB));
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}
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/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB reg_value = value / step << 6 + value % step ; step = 6 * 8*/
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static uint16_t aw883xx_db_val_to_reg(uint16_t value)
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{
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return (((value / AW_PID_2049_VOLUME_STEP_DB) << AW_PID_2049_VOL_6DB_START) +
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(value % AW_PID_2049_VOLUME_STEP_DB));
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}
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static int aw883xx_set_volume(struct aw883xx *aw883xx, uint16_t value)
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{
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uint16_t reg_value = 0;
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uint16_t real_value = aw883xx_db_val_to_reg(value);
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/* cal real value */
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aw883xx_reg_read(aw883xx, AW_PID_2049_SYSCTRL2_REG, ®_value);
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aw_dev_dbg(aw883xx->dev, "value 0x%x , reg:0x%x", value, real_value);
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/*[15 : 6] volume*/
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real_value = (real_value << AW_PID_2049_VOL_START_BIT) | (reg_value & AW_PID_2049_VOL_MASK);
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/* write value */
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aw883xx_reg_write(aw883xx, AW_PID_2049_SYSCTRL2_REG, real_value);
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return 0;
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}
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static int aw883xx_get_volume(struct aw883xx *aw883xx, uint16_t *value)
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{
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uint16_t reg_value = 0;
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uint16_t real_value = 0;
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/* read value */
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aw883xx_reg_read(aw883xx, AW_PID_2049_SYSCTRL2_REG, ®_value);
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/*[15 : 6] volume*/
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real_value = reg_value >> AW_PID_2049_VOL_START_BIT;
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real_value = aw_pid_2049_reg_val_to_db(real_value);
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*value = real_value;
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return 0;
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}
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static int aw_pid_2049_set_volume(struct aw_device *aw_dev, uint16_t value)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_set_volume(aw883xx, value);
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}
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static int aw_pid_2049_get_volume(struct aw_device *aw_dev, uint16_t *value)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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return aw883xx_get_volume(aw883xx, value);
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}
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static void aw_pid_2049_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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aw_dev_dbg(aw883xx->dev, "enter");
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if (flag) {
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aw883xx_reg_write_bits(aw883xx, AW_PID_2049_I2SCFG1_REG,
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AW_PID_2049_I2STXEN_MASK,
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AW_PID_2049_I2STXEN_ENABLE_VALUE);
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} else {
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aw883xx_reg_write_bits(aw883xx, AW_PID_2049_I2SCFG1_REG,
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AW_PID_2049_I2STXEN_MASK,
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AW_PID_2049_I2STXEN_DISABLE_VALUE);
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}
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}
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static void aw_pid_2049_set_cfg_f0_fs(struct aw_device *aw_dev, uint32_t *f0_fs)
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{
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uint16_t rate_data = 0;
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uint32_t fs = 0;
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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aw_dev_dbg(aw883xx->dev, "enter");
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aw883xx_reg_read(aw883xx, AW_PID_2049_I2SCTRL_REG, &rate_data);
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switch (rate_data & (~AW_PID_2049_I2SSR_MASK)) {
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case AW_PID_2049_I2SSR_8_KHZ_VALUE:
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fs = 8000;
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break;
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case AW_PID_2049_I2SSR_16_KHZ_VALUE:
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fs = 16000;
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break;
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case AW_PID_2049_I2SSR_32_KHZ_VALUE:
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fs = 32000;
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break;
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case AW_PID_2049_I2SSR_44_KHZ_VALUE:
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fs = 44000;
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break;
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case AW_PID_2049_I2SSR_48_KHZ_VALUE:
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fs = 48000;
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break;
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case AW_PID_2049_I2SSR_96_KHZ_VALUE:
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fs = 96000;
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break;
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case AW_PID_2049_I2SSR_192KHZ_VALUE:
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fs = 192000;
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break;
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default:
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fs = 48000;
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aw_dev_err(aw883xx->dev,
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"rate can not support, use default 48k");
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break;
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}
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aw_dev_dbg(aw883xx->dev, "get i2s fs:%d", fs);
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*f0_fs = fs / 8;
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aw883xx_dsp_write(aw883xx,
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AW_PID_2049_DSP_REG_CFGF0_FS, *f0_fs, AW_DSP_32_DATA);
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}
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static bool aw_pid_2049_check_rd_access(int reg)
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{
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if (reg >= AW_PID_2049_REG_MAX)
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return false;
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if (aw_pid_2049_reg_access[reg] & REG_RD_ACCESS)
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return true;
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else
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return false;
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}
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static bool aw_pid_2049_check_wr_access(int reg)
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{
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if (reg >= AW_PID_2049_REG_MAX)
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return false;
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if (aw_pid_2049_reg_access[reg] & REG_WR_ACCESS)
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return true;
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else
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return false;
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}
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static int aw_pid_2049_get_reg_num(void)
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{
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return AW_PID_2049_REG_MAX;
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}
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static int aw_pid_2049_get_hw_mon_st(struct aw_device *aw_dev,
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bool *is_enable, uint8_t *temp_flag)
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{
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int ret = 0;
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uint32_t vbat_en = 0;
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uint32_t temp_en = 0;
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uint32_t temp_switch = 0;
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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ret = aw883xx_dsp_read(aw883xx,
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AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG, &vbat_en, AW_DSP_16_DATA);
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if (ret < 0) {
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aw_dev_err(aw883xx->dev, "read hardware monitor status failed");
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return ret;
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}
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ret = aw883xx_dsp_read(aw883xx,
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AW_PID_2049_DSP_REG_TEMP_SWITCH, &temp_en, AW_DSP_16_DATA);
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if (ret < 0) {
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aw_dev_err(aw883xx->dev, "read hardware temp switch failed");
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return ret;
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}
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temp_switch = temp_en;
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vbat_en &= (~AW_PID_2049_DSP_MONITOR_MASK);
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temp_en &= (~AW_PID_2049_DSP_TEMP_PEAK_MASK);
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temp_switch &= (~AW_PID_2049_DSP_TEMP_SEL_FLAG);
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if (vbat_en || temp_en)
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*is_enable = true;
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else
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*is_enable = false;
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if (temp_switch)
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*temp_flag = AW_EXTERNAL_TEMP;
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else
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*temp_flag = AW_INTERNAL_TEMP;
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return 0;
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}
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static int aw_pid_2049_cali_get_iv_st(struct aw_device *aw_dev)
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{
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struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
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int ret;
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uint16_t reg_data = 0;
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int i;
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aw_dev_info(aw_dev->dev, "enter");
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for (i = 0; i < AW_GET_IV_CNT_MAX; i++) {
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ret = aw883xx_reg_read(aw883xx, AW_PID_2049_ASR1_REG, ®_data);
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if (ret < 0) {
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aw_dev_err(aw883xx->dev,
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"read 0x%x failed", AW_PID_2049_ASR1_REG);
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return ret;
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}
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reg_data &= (~AW_PID_2049_ReAbs_MASK);
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if (!reg_data)
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return 0;
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msleep(30);
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}
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aw_dev_err(aw883xx->dev, "IV data abnormal, please check");
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return -EINVAL;
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}
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static int aw_pid_2049_dsp_fw_check(struct aw_device *aw_dev)
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{
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struct aw_prof_desc *set_prof_desc = NULL;
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struct aw_sec_data_desc *dsp_fw_desc = NULL;
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uint16_t base_addr = AW_PID_2049_DSP_FW_ADDR;
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uint16_t addr = base_addr;
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int ret, i;
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uint32_t dsp_val;
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uint16_t bin_val;
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aw_dev_info(aw_dev->dev, "enter");
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ret = aw_dev_get_prof_data(aw_dev, aw_dev->cur_prof, &set_prof_desc);
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if (ret < 0)
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return ret;
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/*update reg*/
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dsp_fw_desc = &set_prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW];
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for (i = 0; i < AW_FW_CHECK_PART; i++) {
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ret = aw883xx_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA);
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if (ret < 0) {
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aw_dev_err(aw_dev->dev, "dsp read failed");
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return ret;
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}
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bin_val = AW_GET_16_DATA(dsp_fw_desc->data[2 * (addr - base_addr)],
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dsp_fw_desc->data[2 * (addr - base_addr) + 1]);
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if (dsp_val != bin_val) {
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aw_dev_err(aw_dev->dev, "check failed, addr[0x%x], read[0x%x] != bindata[0x%x]",
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addr, dsp_val, bin_val);
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return -EINVAL;
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}
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addr += (dsp_fw_desc->len / 2) / AW_FW_CHECK_PART;
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if ((addr - base_addr) > dsp_fw_desc->len) {
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aw_dev_err(aw_dev->dev, "check failed, addr[0x%x] too large", addr);
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return -EINVAL;
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}
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}
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aw_dev_info(aw_dev->dev, "dsp fw check success");
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return 0;
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}
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static int aw883xx_dev_init(struct aw883xx *aw883xx)
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{
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struct aw_device *aw_pa = NULL;
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aw_pa = devm_kzalloc(aw883xx->dev, sizeof(struct aw_device), GFP_KERNEL);
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if (aw_pa == NULL) {
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aw_dev_err(aw883xx->dev, "dev kalloc failed");
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return -ENOMEM;
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}
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/*call aw device init func*/
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aw_pa->acf = NULL;
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aw_pa->prof_info.prof_desc = NULL;
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aw_pa->prof_info.count = 0;
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aw_pa->prof_info.prof_type = AW_DEV_NONE_TYPE_ID;
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aw_pa->channel = 0;
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aw_pa->i2c_lock = &aw883xx->i2c_lock;
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aw_pa->i2c = aw883xx->i2c;
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aw_pa->fw_status = AW_DEV_FW_FAILED;
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aw_pa->fade_step = AW_PID_2049_VOLUME_STEP_DB;
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aw_pa->re_range.re_min_default = AW_RE_MIN;
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aw_pa->re_range.re_max_default = AW_RE_MAX;
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aw_pa->monitor_desc.hw_monitor_delay = AW_HW_MONITOR_DELAY;
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aw_pa->chip_id = aw883xx->chip_id;
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aw_pa->private_data = (void *)aw883xx;
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aw_pa->dev = aw883xx->dev;
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aw_pa->ops.aw_get_version = aw883xx_get_version;
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aw_pa->ops.aw_i2c_writes = aw883xx_dev_i2c_writes;
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aw_pa->ops.aw_i2c_write = aw883xx_dev_i2c_write;
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aw_pa->ops.aw_reg_write = aw883xx_dev_reg_write;
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aw_pa->ops.aw_reg_write_bits = aw883xx_dev_reg_write_bits;
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aw_pa->ops.aw_i2c_read = aw883xx_dev_i2c_read;
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aw_pa->ops.aw_reg_read = aw883xx_dev_reg_read;
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aw_pa->ops.aw_dsp_read = aw883xx_dev_dsp_read;
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aw_pa->ops.aw_dsp_write = aw883xx_dev_dsp_write;
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aw_pa->ops.aw_get_dev_num = aw883xx_get_dev_num;
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aw_pa->ops.aw_get_volume = aw_pid_2049_get_volume;
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aw_pa->ops.aw_set_volume = aw_pid_2049_set_volume;
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aw_pa->ops.aw_reg_val_to_db = aw_pid_2049_reg_val_to_db;
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aw_pa->ops.aw_check_rd_access = aw_pid_2049_check_rd_access;
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aw_pa->ops.aw_check_wr_access = aw_pid_2049_check_wr_access;
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aw_pa->ops.aw_get_reg_num = aw_pid_2049_get_reg_num;
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aw_pa->ops.aw_i2s_tx_enable = aw_pid_2049_i2s_tx_enable;
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aw_pa->ops.aw_get_hw_mon_st = aw_pid_2049_get_hw_mon_st;
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aw_pa->ops.aw_cali_svc_get_iv_st = aw_pid_2049_cali_get_iv_st;
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aw_pa->ops.aw_set_cfg_f0_fs = aw_pid_2049_set_cfg_f0_fs;
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aw_pa->ops.aw_dsp_fw_check = aw_pid_2049_dsp_fw_check;
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aw_pa->int_desc.mask_reg = AW_PID_2049_SYSINTM_REG;
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aw_pa->int_desc.mask_default = AW_PID_2049_SYSINTM_DEFAULT;
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aw_pa->int_desc.int_mask = AW_PID_2049_SYSINTM_DEFAULT;
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aw_pa->int_desc.st_reg = AW_PID_2049_SYSINT_REG;
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aw_pa->int_desc.intst_mask = AW_PID_2049_BIT_SYSINT_CHECK;
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aw_pa->pwd_desc.reg = AW_PID_2049_SYSCTRL_REG;
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aw_pa->pwd_desc.mask = AW_PID_2049_PWDN_MASK;
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aw_pa->pwd_desc.enable = AW_PID_2049_PWDN_POWER_DOWN_VALUE;
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aw_pa->pwd_desc.disable = AW_PID_2049_PWDN_WORKING_VALUE;
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aw_pa->mute_desc.reg = AW_PID_2049_SYSCTRL_REG;
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aw_pa->mute_desc.mask = AW_PID_2049_HMUTE_MASK;
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aw_pa->mute_desc.enable = AW_PID_2049_HMUTE_ENABLE_VALUE;
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aw_pa->mute_desc.disable = AW_PID_2049_HMUTE_DISABLE_VALUE;
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aw_pa->vcalb_desc.vcalb_dsp_reg = AW_PID_2049_DSP_REG_VCALB;
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aw_pa->vcalb_desc.data_type = AW_DSP_16_DATA;
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aw_pa->vcalb_desc.vcal_factor = AW_PID_2049_VCAL_FACTOR;
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aw_pa->vcalb_desc.cabl_base_value = AW_PID_2049_CABL_BASE_VALUE;
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aw_pa->vcalb_desc.vscal_factor = AW_PID_2049_VSCAL_FACTOR;
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aw_pa->vcalb_desc.iscal_factor = AW_PID_2049_ISCAL_FACTOR;
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aw_pa->vcalb_desc.vcalb_adj_shift = AW_PID_2049_VCALB_ADJ_FACTOR;
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aw_pa->vcalb_desc.icalk_value_factor = AW_PID_2049_ICABLK_FACTOR;
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aw_pa->vcalb_desc.icalk_reg = AW_PID_2049_EFRM2_REG;
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aw_pa->vcalb_desc.icalk_reg_mask = AW_PID_2049_EF_ISN_GESLP_MASK;
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aw_pa->vcalb_desc.icalk_sign_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_MASK;
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aw_pa->vcalb_desc.icalk_neg_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_NEG;
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aw_pa->vcalb_desc.vcalk_reg = AW_PID_2049_EFRH_REG;
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aw_pa->vcalb_desc.vcalk_reg_mask = AW_PID_2049_EF_VSN_GESLP_MASK;
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aw_pa->vcalb_desc.vcalk_sign_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_MASK;
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aw_pa->vcalb_desc.vcalk_neg_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_NEG;
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aw_pa->vcalb_desc.vcalk_value_factor = AW_PID_2049_VCABLK_FACTOR;
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aw_pa->vcalb_desc.vcalk_shift = AW_PID_2049_EF_VSENSE_GAIN_SHIFT;
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aw_pa->vcalb_desc.vcalb_vsense_reg = AW_PID_2049_I2SCFG3_REG;
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aw_pa->vcalb_desc.vcalk_vdsel_mask = AW_PID_2049_VDSEL_MASK;
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aw_pa->vcalb_desc.vcalk_value_factor_vsense_in = AW_PID_2049_VCABLK_FACTOR_DAC;
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aw_pa->vcalb_desc.vscal_factor_vsense_in = AW_PID_2049_VSCAL_FACTOR_DAC;
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aw_pa->vcalb_desc.vcalk_dac_shift = AW_PID_2049_EF_DAC_GESLP_SHIFT;
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aw_pa->vcalb_desc.vcalk_dac_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_MASK;
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aw_pa->vcalb_desc.vcalk_dac_neg_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_NEG;
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aw_pa->sysst_desc.reg = AW_PID_2049_SYSST_REG;
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aw_pa->sysst_desc.st_check = AW_PID_2049_BIT_SYSST_CHECK;
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aw_pa->sysst_desc.st_mask = AW_PID_2049_BIT_SYSST_CHECK_MASK;
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aw_pa->sysst_desc.pll_check = AW_PID_2049_BIT_PLL_CHECK;
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aw_pa->sysst_desc.dsp_check = AW_PID_2049_DSPS_NORMAL_VALUE;
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aw_pa->sysst_desc.dsp_mask = AW_PID_2049_DSPS_MASK;
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aw_pa->profctrl_desc.reg = AW_PID_2049_SYSCTRL_REG;
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aw_pa->profctrl_desc.mask = AW_PID_2049_RCV_MODE_MASK;
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aw_pa->profctrl_desc.rcv_mode_val = AW_PID_2049_RCV_MODE_RECEIVER_VALUE;
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aw_pa->volume_desc.reg = AW_PID_2049_SYSCTRL2_REG;
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aw_pa->volume_desc.mask = AW_PID_2049_VOL_MASK;
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aw_pa->volume_desc.shift = AW_PID_2049_VOL_START_BIT;
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aw_pa->volume_desc.mute_volume = AW_PID_2049_MUTE_VOL;
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aw_pa->dsp_en_desc.reg = AW_PID_2049_SYSCTRL_REG;
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aw_pa->dsp_en_desc.mask = AW_PID_2049_DSPBY_MASK;
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aw_pa->dsp_en_desc.enable = AW_PID_2049_DSPBY_WORKING_VALUE;
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aw_pa->dsp_en_desc.disable = AW_PID_2049_DSPBY_BYPASS_VALUE;
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aw_pa->memclk_desc.reg = AW_PID_2049_DBGCTRL_REG;
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aw_pa->memclk_desc.mask = AW_PID_2049_MEM_CLKSEL_MASK;
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aw_pa->memclk_desc.mcu_hclk = AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE;
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aw_pa->memclk_desc.osc_clk = AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE;
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aw_pa->watch_dog_desc.reg = AW_PID_2049_WDT_REG;
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aw_pa->watch_dog_desc.mask = AW_PID_2049_WDT_CNT_MASK;
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aw_pa->dsp_mem_desc.dsp_madd_reg = AW_PID_2049_DSPMADD_REG;
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aw_pa->dsp_mem_desc.dsp_mdat_reg = AW_PID_2049_DSPMDAT_REG;
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aw_pa->dsp_mem_desc.dsp_cfg_base_addr = AW_PID_2049_DSP_CFG_ADDR;
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aw_pa->dsp_mem_desc.dsp_fw_base_addr = AW_PID_2049_DSP_FW_ADDR;
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aw_pa->voltage_desc.reg = AW_PID_2049_VBAT_REG;
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aw_pa->voltage_desc.vbat_range = AW_PID_2049_VBAT_RANGE;
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aw_pa->voltage_desc.int_bit = AW_PID_2049_INT_10BIT;
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aw_pa->temp_desc.reg = AW_PID_2049_TEMP_REG;
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aw_pa->temp_desc.sign_mask = AW_PID_2049_TEMP_SIGN_MASK;
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aw_pa->temp_desc.neg_mask = AW_PID_2049_TEMP_NEG_MASK;
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aw_pa->vmax_desc.dsp_reg = AW_PID_2049_DSP_REG_VMAX;
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aw_pa->vmax_desc.data_type = AW_DSP_16_DATA;
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|
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aw_pa->ipeak_desc.reg = AW_PID_2049_SYSCTRL2_REG;
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aw_pa->ipeak_desc.mask = AW_PID_2049_BST_IPEAK_MASK;
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|
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aw_pa->soft_rst.reg = AW_PID_2049_ID_REG;
|
|
aw_pa->soft_rst.reg_value = AW_PID_2049_SOFT_RESET_VALUE;
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aw_pa->dsp_vol_desc.reg = AW_PID_2049_DSPCFG_REG;
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aw_pa->dsp_vol_desc.mask = AW_PID_2049_DSP_VOL_MASK;
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aw_pa->dsp_vol_desc.mute_st = AW_PID_2049_DSP_VOL_MUTE;
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aw_pa->dsp_vol_desc.noise_st = AW_PID_2049_DSP_VOL_NOISE_ST;
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aw_pa->amppd_desc.reg = AW_PID_2049_SYSCTRL_REG;
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aw_pa->amppd_desc.mask = AW_PID_2049_AMPPD_MASK;
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aw_pa->amppd_desc.enable = AW_PID_2049_AMPPD_POWER_DOWN_VALUE;
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aw_pa->amppd_desc.disable = AW_PID_2049_AMPPD_WORKING_VALUE;
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|
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aw_pa->spkr_temp_desc.reg = AW_PID_2049_ASR2_REG;
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|
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/*32-bit data types need bypass dsp*/
|
|
aw_pa->ra_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RA;
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|
aw_pa->ra_desc.data_type = AW_DSP_32_DATA;
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|
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|
/*32-bit data types need bypass dsp*/
|
|
aw_pa->cali_cfg_desc.actampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH;
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|
aw_pa->cali_cfg_desc.actampth_data_type = AW_DSP_32_DATA;
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/*32-bit data types need bypass dsp*/
|
|
aw_pa->cali_cfg_desc.noiseampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH;
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|
aw_pa->cali_cfg_desc.noiseampth_data_type = AW_DSP_32_DATA;
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aw_pa->cali_cfg_desc.ustepn_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN;
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aw_pa->cali_cfg_desc.ustepn_data_type = AW_DSP_16_DATA;
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aw_pa->cali_cfg_desc.alphan_reg = AW_PID_2049_DSP_REG_CFG_RE_ALPHA;
|
|
aw_pa->cali_cfg_desc.alphan_data_type = AW_DSP_16_DATA;
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|
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|
/*32-bit data types need bypass dsp*/
|
|
aw_pa->adpz_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RE;
|
|
aw_pa->adpz_re_desc.data_type = AW_DSP_32_DATA;
|
|
aw_pa->adpz_re_desc.shift = AW_PID_2049_DSP_RE_SHIFT;
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|
|
|
aw_pa->t0_desc.dsp_reg = AW_PID_2049_DSP_CFG_ADPZ_T0;
|
|
aw_pa->t0_desc.data_type = AW_DSP_16_DATA;
|
|
aw_pa->t0_desc.coilalpha_reg = AW_PID_2049_DSP_CFG_ADPZ_COILALPHA;
|
|
aw_pa->t0_desc.coil_type = AW_DSP_16_DATA;
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|
|
|
aw_pa->ste_re_desc.shift = AW_PID_2049_DSP_REG_CALRE_SHIFT;
|
|
aw_pa->ste_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CALRE;
|
|
aw_pa->ste_re_desc.data_type = AW_DSP_16_DATA;
|
|
|
|
aw_pa->noise_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG;
|
|
aw_pa->noise_desc.data_type = AW_DSP_16_DATA;
|
|
aw_pa->noise_desc.mask = AW_PID_2049_DSP_REG_NOISE_MASK;
|
|
|
|
aw_pa->f0_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_F0;
|
|
aw_pa->f0_desc.shift = AW_PID_2049_DSP_F0_SHIFT;
|
|
aw_pa->f0_desc.data_type = AW_DSP_16_DATA;
|
|
|
|
/*32-bit data types need bypass dsp*/
|
|
aw_pa->cfgf0_fs_desc.dsp_reg = AW_PID_2049_DSP_REG_CFGF0_FS;
|
|
aw_pa->cfgf0_fs_desc.data_type = AW_DSP_32_DATA;
|
|
|
|
aw_pa->q_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_Q;
|
|
aw_pa->q_desc.shift = AW_PID_2049_DSP_Q_SHIFT;
|
|
aw_pa->q_desc.data_type = AW_DSP_16_DATA;
|
|
|
|
/*32-bit data types need bypass dsp*/
|
|
aw_pa->dsp_crc_desc.dsp_reg = AW_PID_2049_DSP_REG_CRC_ADDR;
|
|
aw_pa->dsp_crc_desc.data_type = AW_DSP_32_DATA;
|
|
|
|
aw_pa->dsp_crc_desc.ctl_reg = AW_PID_2049_HAGCCFG7_REG;
|
|
aw_pa->dsp_crc_desc.ctl_mask = AW_PID_2049_AGC_DSP_CTL_MASK;
|
|
aw_pa->dsp_crc_desc.ctl_enable = AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE;
|
|
aw_pa->dsp_crc_desc.ctl_disable = AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE;
|
|
|
|
aw_pa->cco_mux_desc.reg = AW_PID_2049_PLLCTRL1_REG;
|
|
aw_pa->cco_mux_desc.mask = AW_PID_2049_CCO_MUX_MASK;
|
|
aw_pa->cco_mux_desc.divider = AW_PID_2049_CCO_MUX_DIVIDED_VALUE;
|
|
aw_pa->cco_mux_desc.bypass = AW_PID_2049_CCO_MUX_BYPASS_VALUE;
|
|
|
|
/*hw monitor temp reg*/
|
|
aw_pa->hw_temp_desc.dsp_reg = AW_PID_2049_DSP_REG_TEMP_ADDR;
|
|
aw_pa->hw_temp_desc.data_type = AW_DSP_16_DATA;
|
|
|
|
aw_pa->chansel_desc.rxchan_reg = AW_PID_2049_I2SCTRL_REG;
|
|
aw_pa->chansel_desc.rxchan_mask = AW_PID_2049_CHSEL_MASK;
|
|
aw_pa->chansel_desc.txchan_reg = AW_PID_2049_I2SCFG1_REG;
|
|
aw_pa->chansel_desc.txchan_mask = AW_PID_2049_I2SCHS_MASK;
|
|
|
|
aw_pa->chansel_desc.rx_left = AW_PID_2049_CHSEL_LEFT_VALUE;
|
|
aw_pa->chansel_desc.rx_right = AW_PID_2049_CHSEL_RIGHT_VALUE;
|
|
aw_pa->chansel_desc.tx_left = AW_PID_2049_I2SCHS_LEFT_VALUE;
|
|
aw_pa->chansel_desc.tx_right = AW_PID_2049_I2SCHS_RIGHT_VALUE;
|
|
|
|
aw_pa->tx_en_desc.tx_en_mask = AW_PID_2049_I2STXEN_MASK;
|
|
aw_pa->tx_en_desc.tx_disable = AW_PID_2049_I2STXEN_DISABLE_VALUE;
|
|
|
|
aw_pa->cali_delay_desc.dsp_reg = AW_PID_2049_DSP_CALI_F0_DELAY;
|
|
aw_pa->cali_delay_desc.data_type = AW_DSP_16_DATA;
|
|
|
|
aw_pa->dsp_st_desc.dsp_reg_s1 = AW_PID_2049_DSP_ST_S1;
|
|
aw_pa->dsp_st_desc.dsp_reg_e1 = AW_PID_2049_DSP_ST_E1;
|
|
aw_pa->dsp_st_desc.dsp_reg_s2 = AW_PID_2049_DSP_ST_S2;
|
|
aw_pa->dsp_st_desc.dsp_reg_e2 = AW_PID_2049_DSP_ST_E2;
|
|
|
|
aw_device_probe(aw_pa);
|
|
|
|
aw883xx->aw_pa = aw_pa;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aw883xx_init(struct aw883xx *aw883xx)
|
|
{
|
|
if (aw883xx->chip_id == AW883XX_PID_2049) {
|
|
return aw883xx_dev_init(aw883xx);
|
|
} else {
|
|
aw_dev_err(aw883xx->dev, "unsupported device");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|