176 lines
3.7 KiB
ArmAsm
176 lines
3.7 KiB
ArmAsm
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "rv1106_pm.h"
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#define RV1106_GPIO0_INT_ST 0xff380050
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#define RV1106_PMUGRF_OS_REG10 0xff020228
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#define RV1106_PMUGRF_SOC_CON4 0xff020010
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#define RV1106_CRU_GLB_SRST_FST 0xff3b0c08
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#define RV1106_CRU_GLB_RST_CON_ADDR 0xff3b0c10
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#define CRU_FST_RST_PMU_VAL 0x000c000c
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#if RV1106_SLEEP_DEBUG
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/********************* console used for sleep.S ******************************/
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#define UART_REG_DLL (0x00)
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#define UART_REG_DLH (0x04)
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#define UART_REG_IER (0x04)
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#define UART_REG_FCR (0x08)
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#define UART_REG_LCR (0x0c)
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#define UART_REG_MCR (0x10)
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#define UARTLCR_DLAB (1 << 7)
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#define UARTFCR_DMAEN (1 << 3)
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#define UARTFCR_FIFOEN (1 << 0)
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#define CONSOLE_UART_BASE 0xff4c0000
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#define CONSOLE_CLKRATE 24000000
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#define CONSOLE_BAUDRATE 115200
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#define GPIO1_B_IOMUX 0xff538008
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#define GRF_GPIO1D_VAL 0xff002200
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.macro early_console_init
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ldr r0, =GPIO1_B_IOMUX
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ldr r1, =GRF_GPIO1D_VAL
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str r1, [r0]
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ldr r0, =CONSOLE_UART_BASE
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ldr r1, =CONSOLE_CLKRATE
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ldr r2, =CONSOLE_BAUDRATE
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/* Program the baudrate */
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/* Divisor = Uart clock / (16 * baudrate) */
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mov r1, #0xd
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mov r2, #0x0
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ldr r3, [r0, #UART_REG_LCR]
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orr r3, r3, #UARTLCR_DLAB
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str r3, [r0, #UART_REG_LCR] /* enable DLL, DLH programming */
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str r1, [r0, #UART_REG_DLL] /* program DLL */
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str r2, [r0, #UART_REG_DLH] /* program DLH */
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mov r2, #~UARTLCR_DLAB
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and r3, r3, r2
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str r3, [r0, #UART_REG_LCR] /* disable DLL, DLH programming */
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/* 8n1 */
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mov r3, #3
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str r3, [r0, #UART_REG_LCR]
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/* no interrupt */
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mov r3, #0
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str r3, [r0, #UART_REG_IER]
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/* enable fifo, DMA */
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mov r3, #(UARTFCR_FIFOEN | UARTFCR_DMAEN)
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str r3, [r0, #UART_REG_FCR]
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/* DTR + RTS */
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mov r3, #3
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str r3, [r0, #UART_REG_MCR]
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mov r0, #1
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dsb sy
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.endm
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.macro early_console_putc ch
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ldr r0, =CONSOLE_UART_BASE
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mov r1, #\ch
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str r1, [r0]
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.endm
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/********************* console used for sleep.S ******************************/
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#endif
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.align 2
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.arm
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ENTRY(rockchip_slp_cpu_resume)
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#if RV1106_SLEEP_DEBUG
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early_console_init
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/* print 'A' */
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early_console_putc 0x41
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#endif
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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#if RV1106_WAKEUP_TO_SYSTEM_RESET
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/* save gpio wakeup src */
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ldr r0, =RV1106_PMUGRF_OS_REG10
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ldr r1, =RV1106_GPIO0_INT_ST
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ldr r1, [r1]
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str r1, [r0]
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/* enable first reset trigger pmu reset */
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ldr r0, =RV1106_CRU_GLB_RST_CON_ADDR
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ldr r1, =CRU_FST_RST_PMU_VAL
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str r1, [r0]
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/* clear pmu reset hold */
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ldr r0, =RV1106_PMUGRF_SOC_CON4
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ldr r1, =0xffff0000
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str r1, [r0]
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add r0, r0, #4
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str r1, [r0]
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/* first reset */
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ldr r0, =RV1106_CRU_GLB_SRST_FST
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mov r1, #0xfdb9
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str r1, [r0]
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b .
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#endif
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ldr r3, rkpm_bootdata_l2ctlr_f
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cmp r3, #0
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beq sp_set
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ldr r3, rkpm_bootdata_l2ctlr
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mcr p15, 1, r3, c9, c0, 2
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sp_set:
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ldr sp, rkpm_bootdata_cpusp
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ldr r0, rkpm_ddr_data
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ldr r1, rkpm_ddr_func
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cmp r1, #0
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beq boot
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blx r1
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boot:
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ldr r1, rkpm_bootdata_cpu_code
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bx r1
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ENDPROC(rockchip_slp_cpu_resume)
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/* Parameters filled in by the kernel */
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/* Flag for whether to restore L2CTLR on resume */
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.global rkpm_bootdata_l2ctlr_f
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rkpm_bootdata_l2ctlr_f:
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.long 0
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/* Saved L2CTLR to restore on resume */
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.global rkpm_bootdata_l2ctlr
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rkpm_bootdata_l2ctlr:
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.long 0
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/* CPU resume SP addr */
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.globl rkpm_bootdata_cpusp
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rkpm_bootdata_cpusp:
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.long 0
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/* CPU resume function (physical address) */
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.globl rkpm_bootdata_cpu_code
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rkpm_bootdata_cpu_code:
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.long 0
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/* ddr resume data */
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.globl rkpm_ddr_data
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rkpm_ddr_data:
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.long 0
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/* ddr resume function (physical address) */
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.globl rkpm_ddr_func
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rkpm_ddr_func:
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.long 0
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ENTRY(rv1106_bootram_sz)
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.word . - rockchip_slp_cpu_resume
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