117 lines
3.5 KiB
Plaintext
117 lines
3.5 KiB
Plaintext
Rockchip SoC Camera Interface
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----------------------------------------------
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Rockchip CIF is a camera interface for the Rockchip series of SoCs
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like px30, rk3288, rk312x, rk1808, RV1108 to receive frame data from camera or CCIR656 encoder,
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and transfer the data into system main memory by AXI bus.
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Required properties:
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- compatible: value should be one of the following
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"rockchip,px30-cif";
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"rockchip,rk1808-cif";
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"rockchip,rk3128-cif";
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"rockchip,rk3288-cif";
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- reg : offset and length of the register set for the device.
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- interrupts: should contain cif interrupt.
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- clocks: phandle to the required clocks.
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- clock-names: required clock name.
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Optional properties:
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- iommus: iommu node attached to cif if exist.
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- resets: CRU reset of cif if exist.
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port node
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-------------------
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The device node should contain one 'port' child node with child 'endpoint'
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nodes, according to the bindings defined in Documentation/devicetree/bindings/
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media/video-interfaces.txt.
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- endpoint(parallel):
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- remote-endpoint: Connecting to a sensor with a parallel video bus or a mipi csi2 bus.
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- parallel_bus properties: Refer to Documentation/devicetree/bindings/
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media/video-interfaces.txt.
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- mipi csi2 bus properties: Refer to Documentation/devicetree/bindings/
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media/video-interfaces.txt.
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The port node must contain at least one endpoint.
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It could have multiple endpoints, but please note the hardware don't support
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two sensors work at a time, they are supposed to work asynchronously.
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Device node example
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-------------------
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cif: cif@ff490000 {
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compatible = "rockchip,px30-cif";
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reg = <0x0 0xff490000 0x0 0x200>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>;
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clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out";
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resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
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reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
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power-domains = <&power PX30_PD_VI>;
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iommus = <&vip_mmu>;
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status = "okay";
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port {
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cif_in: endpoint {
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remote-endpoint = <&gc2155_out>;
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vsync-active = <0>;
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hsync-active = <1>;
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};
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};
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};
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cif: cif@ffae0000 {
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compatible = "rockchip,rk1808-cif";
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reg = <0x0 0xffae0000 0x0 0x200>, <0x0 0xffb10000 0x0 0x100>;
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reg-names = "cif_regs", "csihost_regs";
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>,
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<&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>,
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<&cru PCLK_CSI2HOST>;
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clock-names = "aclk_cif", "dclk_cif",
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"hclk_cif", "sclk_cif_out",
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"pclk_csi2host";
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resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
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<&cru SRST_CIF_I>, <&cru SRST_CIF_D>,
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<&cru SRST_CIF_PCLKIN>;
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reset-names = "rst_cif_a", "rst_cif_h",
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"rst_cif_i", "rst_cif_d",
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"rst_cif_pclkin";
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power-domains = <&power RK1808_PD_VIO>;
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iommus = <&cif_mmu>;
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status = "okay";
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port {
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cif_in: endpoint@0 {
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remote-endpoint = <&dphy_rx_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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cif: cif@1010a000 {
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compatible = "rockchip,rk3128-cif";
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reg = <0x1010a000 0x200>;
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clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
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<&cru SCLK_CIF_OUT>;
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clock-names = "aclk_cif", "hclk_cif",
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"sclk_cif_out";
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resets = <&cru SRST_CIF0>;
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reset-names = "rst_cif";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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/* px3se has not iommu attached */
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/* iommus = <&cif_mmu>; */
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power-domains = <&power RK3128_PD_VIO>;
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status = "okay";
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port {
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cif_in: endpoint {
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remote-endpoint = <&adv7181_out>;
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vsync-active = <0>;
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hsync-active = <1>;
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};
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};
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};
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