101 lines
2.8 KiB
YAML
101 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Read Direct Memory Access
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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- Moudy Ho <moudy.ho@mediatek.com>
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description: |
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MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
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It contains one line buffer to store the sufficient pixel data, and
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must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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items:
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- const: mediatek,mt8183-mdp3-rdma
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reg:
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maxItems: 1
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mediatek,gce-client-reg:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property. Each GCE subsys id is mapping to
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a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
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mediatek,gce-events:
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description:
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The event id which is mapping to the specific hardware event signal
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to gce. The event id is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: RDMA clock
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- description: RSZ clock
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iommus:
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maxItems: 1
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mboxes:
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items:
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- description: used for 1st data pipe from RDMA
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- description: used for 2nd data pipe from RDMA
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'#dma-cells':
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const: 1
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required:
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- compatible
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- reg
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- mediatek,gce-client-reg
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- mediatek,gce-events
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- power-domains
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- clocks
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- iommus
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- mboxes
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- '#dma-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/memory/mt8183-larb-port.h>
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dma-controller@14001000 {
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compatible = "mediatek,mt8183-mdp3-rdma";
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reg = <0x14001000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
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<CMDQ_EVENT_MDP_RDMA0_EOF>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MDP_RSZ1>;
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iommus = <&iommu>;
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mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
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<&gce 21 CMDQ_THR_PRIO_LOWEST>;
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#dma-cells = <1>;
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};
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