374 lines
12 KiB
C
374 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PMAC_ZILOG_H__
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#define __PMAC_ZILOG_H__
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/*
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* At most 2 ESCCs with 2 ports each
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*/
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#define MAX_ZS_PORTS 4
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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#define NUM_ZSREGS 17
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struct uart_pmac_port {
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struct uart_port port;
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struct uart_pmac_port *mate;
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#ifdef CONFIG_PPC_PMAC
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/* macio_dev for the escc holding this port (maybe be null on
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* early inited port)
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*/
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struct macio_dev *dev;
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/* device node to this port, this points to one of 2 childs
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* of "escc" node (ie. ch-a or ch-b)
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*/
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struct device_node *node;
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#else
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struct platform_device *pdev;
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#endif
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/* Port type as obtained from device tree (IRDA, modem, ...) */
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int port_type;
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u8 curregs[NUM_ZSREGS];
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unsigned int flags;
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#define PMACZILOG_FLAG_IS_CONS 0x00000001
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#define PMACZILOG_FLAG_IS_KGDB 0x00000002
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#define PMACZILOG_FLAG_MODEM_STATUS 0x00000004
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#define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008
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#define PMACZILOG_FLAG_REGS_HELD 0x00000010
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#define PMACZILOG_FLAG_TX_STOPPED 0x00000020
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#define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
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#define PMACZILOG_FLAG_IS_IRDA 0x00000100
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#define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
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#define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
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#define PMACZILOG_FLAG_IS_OPEN 0x00002000
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#define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
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#define PMACZILOG_FLAG_BREAK 0x00010000
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unsigned char parity_mask;
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unsigned char prev_status;
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volatile u8 __iomem *control_reg;
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volatile u8 __iomem *data_reg;
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unsigned char irq_name[8];
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};
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#define to_pmz(p) ((struct uart_pmac_port *)(p))
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static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
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{
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if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
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return uap;
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return uap->mate;
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}
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/*
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* Register accessors. Note that we don't need to enforce a recovery
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* delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
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* though if we try to use this driver on older machines, we might have
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* to add it back
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*/
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static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
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{
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if (reg != 0)
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writeb(reg, port->control_reg);
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return readb(port->control_reg);
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}
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static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
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{
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if (reg != 0)
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writeb(reg, port->control_reg);
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writeb(value, port->control_reg);
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}
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static inline u8 read_zsdata(struct uart_pmac_port *port)
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{
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return readb(port->data_reg);
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}
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static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
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{
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writeb(data, port->data_reg);
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}
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static inline void zssync(struct uart_pmac_port *port)
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{
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(void)readb(port->control_reg);
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}
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/* Conversion routines to/from brg time constants from/to bits
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* per second.
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*/
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#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
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#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
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#define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
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/* The Zilog register set */
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#define FLAG 0x7e
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/* Write Register 0 */
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#define R0 0 /* Register selects */
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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#define R7P 16
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#define NULLCODE 0 /* Null Code */
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#define POINT_HIGH 0x8 /* Select upper half of registers */
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#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
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#define SEND_ABORT 0x18 /* HDLC Abort */
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#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
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#define RES_Tx_P 0x28 /* Reset TxINT Pending */
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#define ERR_RES 0x30 /* Error Reset */
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#define RES_H_IUS 0x38 /* Reset highest IUS */
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#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
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#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
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#define RES_EOM_L 0xC0 /* Reset EOM latch */
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/* Write Register 1 */
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#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
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#define TxINT_ENAB 0x2 /* Tx Int Enable */
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#define PAR_SPEC 0x4 /* Parity is special condition */
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#define RxINT_DISAB 0 /* Rx Int Disable */
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#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
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#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
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#define INT_ERR_Rx 0x18 /* Int on error only */
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#define RxINT_MASK 0x18
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#define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */
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#define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */
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#define WT_RDY_ENAB 0x80 /* Enable W/Req pin */
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/* Write Register #2 (Interrupt Vector) */
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/* Write Register 3 */
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#define RxENABLE 0x1 /* Rx Enable */
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#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
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#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
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#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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#define ENT_HM 0x10 /* Enter Hunt Mode */
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#define AUTO_ENAB 0x20 /* Auto Enables */
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#define Rx5 0x0 /* Rx 5 Bits/Character */
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#define Rx7 0x40 /* Rx 7 Bits/Character */
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#define Rx6 0x80 /* Rx 6 Bits/Character */
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#define Rx8 0xc0 /* Rx 8 Bits/Character */
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#define RxN_MASK 0xc0
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/* Write Register 4 */
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#define PAR_ENAB 0x1 /* Parity Enable */
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#define PAR_EVEN 0x2 /* Parity Even/Odd* */
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#define SYNC_ENAB 0 /* Sync Modes Enable */
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#define SB1 0x4 /* 1 stop bit/char */
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#define SB15 0x8 /* 1.5 stop bits/char */
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#define SB2 0xc /* 2 stop bits/char */
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#define SB_MASK 0xc
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#define MONSYNC 0 /* 8 Bit Sync character */
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#define BISYNC 0x10 /* 16 bit sync character */
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#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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#define EXTSYNC 0x30 /* External Sync Mode */
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#define X1CLK 0x0 /* x1 clock mode */
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#define X16CLK 0x40 /* x16 clock mode */
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#define X32CLK 0x80 /* x32 clock mode */
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#define X64CLK 0xC0 /* x64 clock mode */
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#define XCLK_MASK 0xC0
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/* Write Register 5 */
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#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
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#define RTS 0x2 /* RTS */
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#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
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#define TxENABLE 0x8 /* Tx Enable */
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#define SND_BRK 0x10 /* Send Break */
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#define Tx5 0x0 /* Tx 5 bits (or less)/character */
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#define Tx7 0x20 /* Tx 7 bits/character */
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#define Tx6 0x40 /* Tx 6 bits/character */
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#define Tx8 0x60 /* Tx 8 bits/character */
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#define TxN_MASK 0x60
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#define DTR 0x80 /* DTR */
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/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
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/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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/* Write Register 7' (Some enhanced feature control) */
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#define ENEXREAD 0x40 /* Enable read of some write registers */
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/* Write Register 8 (transmit buffer) */
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/* Write Register 9 (Master interrupt control) */
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#define VIS 1 /* Vector Includes Status */
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#define NV 2 /* No Vector */
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#define DLC 4 /* Disable Lower Chain */
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#define MIE 8 /* Master Interrupt Enable */
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#define STATHI 0x10 /* Status high */
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#define NORESET 0 /* No reset on write to R9 */
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#define CHRB 0x40 /* Reset channel B */
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#define CHRA 0x80 /* Reset channel A */
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#define FHWRES 0xc0 /* Force hardware reset */
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/* Write Register 10 (misc control bits) */
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#define BIT6 1 /* 6 bit/8bit sync */
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#define LOOPMODE 2 /* SDLC Loop mode */
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#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
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#define MARKIDLE 8 /* Mark/flag on idle */
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#define GAOP 0x10 /* Go active on poll */
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#define NRZ 0 /* NRZ mode */
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#define NRZI 0x20 /* NRZI mode */
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#define FM1 0x40 /* FM1 (transition = 1) */
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#define FM0 0x60 /* FM0 (transition = 0) */
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#define CRCPS 0x80 /* CRC Preset I/O */
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/* Write Register 11 (Clock Mode control) */
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#define TRxCXT 0 /* TRxC = Xtal output */
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#define TRxCTC 1 /* TRxC = Transmit clock */
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#define TRxCBR 2 /* TRxC = BR Generator Output */
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#define TRxCDP 3 /* TRxC = DPLL output */
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#define TRxCOI 4 /* TRxC O/I */
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#define TCRTxCP 0 /* Transmit clock = RTxC pin */
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#define TCTRxCP 8 /* Transmit clock = TRxC pin */
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#define TCBR 0x10 /* Transmit clock = BR Generator output */
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#define TCDPLL 0x18 /* Transmit clock = DPLL output */
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#define RCRTxCP 0 /* Receive clock = RTxC pin */
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#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
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#define RCBR 0x40 /* Receive clock = BR Generator output */
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#define RCDPLL 0x60 /* Receive clock = DPLL output */
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#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
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/* Write Register 12 (lower byte of baud rate generator time constant) */
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/* Write Register 13 (upper byte of baud rate generator time constant) */
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/* Write Register 14 (Misc control bits) */
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#define BRENAB 1 /* Baud rate generator enable */
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#define BRSRC 2 /* Baud rate generator source */
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#define DTRREQ 4 /* DTR/Request function */
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#define AUTOECHO 8 /* Auto Echo */
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#define LOOPBAK 0x10 /* Local loopback */
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#define SEARCH 0x20 /* Enter search mode */
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#define RMC 0x40 /* Reset missing clock */
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#define DISDPLL 0x60 /* Disable DPLL */
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#define SSBR 0x80 /* Set DPLL source = BR generator */
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#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
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#define SFMM 0xc0 /* Set FM mode */
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#define SNRZI 0xe0 /* Set NRZI mode */
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/* Write Register 15 (external/status interrupt control) */
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#define EN85C30 1 /* Enable some 85c30-enhanced registers */
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#define ZCIE 2 /* Zero count IE */
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#define ENSTFIFO 4 /* Enable status FIFO (SDLC) */
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#define DCDIE 8 /* DCD IE */
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#define SYNCIE 0x10 /* Sync/hunt IE */
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#define CTSIE 0x20 /* CTS IE */
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#define TxUIE 0x40 /* Tx Underrun/EOM IE */
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#define BRKIE 0x80 /* Break/Abort IE */
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/* Read Register 0 */
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#define Rx_CH_AV 0x1 /* Rx Character Available */
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#define ZCOUNT 0x2 /* Zero count */
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#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
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#define DCD 0x8 /* DCD */
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#define SYNC_HUNT 0x10 /* Sync/hunt */
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#define CTS 0x20 /* CTS */
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#define TxEOM 0x40 /* Tx underrun */
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#define BRK_ABRT 0x80 /* Break/Abort */
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/* Read Register 1 */
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#define ALL_SNT 0x1 /* All sent */
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/* Residue Data for 8 Rx bits/char programmed */
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#define RES3 0x8 /* 0/3 */
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#define RES4 0x4 /* 0/4 */
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#define RES5 0xc /* 0/5 */
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#define RES6 0x2 /* 0/6 */
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#define RES7 0xa /* 0/7 */
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#define RES8 0x6 /* 0/8 */
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#define RES18 0xe /* 1/8 */
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#define RES28 0x0 /* 2/8 */
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/* Special Rx Condition Interrupts */
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#define PAR_ERR 0x10 /* Parity error */
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#define Rx_OVR 0x20 /* Rx Overrun Error */
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#define CRC_ERR 0x40 /* CRC/Framing Error */
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#define END_FR 0x80 /* End of Frame (SDLC) */
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/* Read Register 2 (channel b only) - Interrupt vector */
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#define CHB_Tx_EMPTY 0x00
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#define CHB_EXT_STAT 0x02
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#define CHB_Rx_AVAIL 0x04
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#define CHB_SPECIAL 0x06
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#define CHA_Tx_EMPTY 0x08
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#define CHA_EXT_STAT 0x0a
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#define CHA_Rx_AVAIL 0x0c
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#define CHA_SPECIAL 0x0e
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#define STATUS_MASK 0x06
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/* Read Register 3 (interrupt pending register) ch a only */
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#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
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#define CHBTxIP 0x2 /* Channel B Tx IP */
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#define CHBRxIP 0x4 /* Channel B Rx IP */
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#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
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#define CHATxIP 0x10 /* Channel A Tx IP */
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#define CHARxIP 0x20 /* Channel A Rx IP */
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/* Read Register 8 (receive data register) */
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/* Read Register 10 (misc status bits) */
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#define ONLOOP 2 /* On loop */
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#define LOOPSEND 0x10 /* Loop sending */
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#define CLK2MIS 0x40 /* Two clocks missing */
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#define CLK1MIS 0x80 /* One clock missing */
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/* Read Register 12 (lower byte of baud rate generator constant) */
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/* Read Register 13 (upper byte of baud rate generator constant) */
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/* Read Register 15 (value of WR 15) */
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/* Misc macros */
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#define ZS_CLEARERR(port) (write_zsreg(port, 0, ERR_RES))
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#define ZS_CLEARFIFO(port) do { \
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read_zsdata(port); \
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read_zsdata(port); \
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read_zsdata(port); \
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} while(0)
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#define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
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#define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
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#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
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#define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
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#define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
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#define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
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#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
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#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
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#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
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#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
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#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
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#endif /* __PMAC_ZILOG_H__ */
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