528 lines
14 KiB
C
528 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*/
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#include <linux/list.h>
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#include "altera_utils.h"
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#include "altera_tse.h"
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#include "altera_sgdmahw.h"
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#include "altera_sgdma.h"
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static void sgdma_setup_descrip(struct sgdma_descrip __iomem *desc,
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struct sgdma_descrip __iomem *ndesc,
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dma_addr_t ndesc_phys,
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dma_addr_t raddr,
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dma_addr_t waddr,
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u16 length,
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int generate_eop,
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int rfixed,
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int wfixed);
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static int sgdma_async_write(struct altera_tse_private *priv,
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struct sgdma_descrip __iomem *desc);
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static int sgdma_async_read(struct altera_tse_private *priv);
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static dma_addr_t
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sgdma_txphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip __iomem *desc);
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static dma_addr_t
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sgdma_rxphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip __iomem *desc);
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static int sgdma_txbusy(struct altera_tse_private *priv);
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static int sgdma_rxbusy(struct altera_tse_private *priv);
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static void
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queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer);
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static void
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queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer);
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static struct tse_buffer *
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dequeue_tx(struct altera_tse_private *priv);
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static struct tse_buffer *
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dequeue_rx(struct altera_tse_private *priv);
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static struct tse_buffer *
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queue_rx_peekhead(struct altera_tse_private *priv);
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int sgdma_initialize(struct altera_tse_private *priv)
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{
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priv->txctrlreg = SGDMA_CTRLREG_ILASTD |
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SGDMA_CTRLREG_INTEN;
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priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP |
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SGDMA_CTRLREG_INTEN |
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SGDMA_CTRLREG_ILASTD;
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INIT_LIST_HEAD(&priv->txlisthd);
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INIT_LIST_HEAD(&priv->rxlisthd);
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priv->rxdescphys = (dma_addr_t) 0;
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priv->txdescphys = (dma_addr_t) 0;
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priv->rxdescphys = dma_map_single(priv->device,
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(void __force *)priv->rx_dma_desc,
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priv->rxdescmem, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(priv->device, priv->rxdescphys)) {
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sgdma_uninitialize(priv);
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netdev_err(priv->dev, "error mapping rx descriptor memory\n");
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return -EINVAL;
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}
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priv->txdescphys = dma_map_single(priv->device,
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(void __force *)priv->tx_dma_desc,
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priv->txdescmem, DMA_TO_DEVICE);
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if (dma_mapping_error(priv->device, priv->txdescphys)) {
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sgdma_uninitialize(priv);
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netdev_err(priv->dev, "error mapping tx descriptor memory\n");
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return -EINVAL;
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}
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/* Initialize descriptor memory to all 0's, sync memory to cache */
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memset_io(priv->tx_dma_desc, 0, priv->txdescmem);
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memset_io(priv->rx_dma_desc, 0, priv->rxdescmem);
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dma_sync_single_for_device(priv->device, priv->txdescphys,
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priv->txdescmem, DMA_TO_DEVICE);
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dma_sync_single_for_device(priv->device, priv->rxdescphys,
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priv->rxdescmem, DMA_TO_DEVICE);
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return 0;
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}
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void sgdma_uninitialize(struct altera_tse_private *priv)
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{
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if (priv->rxdescphys)
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dma_unmap_single(priv->device, priv->rxdescphys,
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priv->rxdescmem, DMA_BIDIRECTIONAL);
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if (priv->txdescphys)
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dma_unmap_single(priv->device, priv->txdescphys,
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priv->txdescmem, DMA_TO_DEVICE);
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}
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/* This function resets the SGDMA controller and clears the
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* descriptor memory used for transmits and receives.
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*/
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void sgdma_reset(struct altera_tse_private *priv)
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{
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/* Initialize descriptor memory to 0 */
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memset_io(priv->tx_dma_desc, 0, priv->txdescmem);
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memset_io(priv->rx_dma_desc, 0, priv->rxdescmem);
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csrwr32(SGDMA_CTRLREG_RESET, priv->tx_dma_csr, sgdma_csroffs(control));
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csrwr32(0, priv->tx_dma_csr, sgdma_csroffs(control));
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csrwr32(SGDMA_CTRLREG_RESET, priv->rx_dma_csr, sgdma_csroffs(control));
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csrwr32(0, priv->rx_dma_csr, sgdma_csroffs(control));
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}
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/* For SGDMA, interrupts remain enabled after initially enabling,
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* so no need to provide implementations for abstract enable
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* and disable
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*/
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void sgdma_enable_rxirq(struct altera_tse_private *priv)
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{
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}
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void sgdma_enable_txirq(struct altera_tse_private *priv)
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{
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}
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void sgdma_disable_rxirq(struct altera_tse_private *priv)
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{
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}
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void sgdma_disable_txirq(struct altera_tse_private *priv)
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{
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}
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void sgdma_clear_rxirq(struct altera_tse_private *priv)
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{
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tse_set_bit(priv->rx_dma_csr, sgdma_csroffs(control),
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SGDMA_CTRLREG_CLRINT);
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}
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void sgdma_clear_txirq(struct altera_tse_private *priv)
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{
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tse_set_bit(priv->tx_dma_csr, sgdma_csroffs(control),
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SGDMA_CTRLREG_CLRINT);
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}
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/* transmits buffer through SGDMA. Returns number of buffers
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* transmitted, 0 if not possible.
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*
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* tx_lock is held by the caller
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*/
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int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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struct sgdma_descrip __iomem *descbase =
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(struct sgdma_descrip __iomem *)priv->tx_dma_desc;
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struct sgdma_descrip __iomem *cdesc = &descbase[0];
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struct sgdma_descrip __iomem *ndesc = &descbase[1];
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/* wait 'til the tx sgdma is ready for the next transmit request */
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if (sgdma_txbusy(priv))
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return 0;
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sgdma_setup_descrip(cdesc, /* current descriptor */
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ndesc, /* next descriptor */
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sgdma_txphysaddr(priv, ndesc),
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buffer->dma_addr, /* address of packet to xmit */
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0, /* write addr 0 for tx dma */
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buffer->len, /* length of packet */
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SGDMA_CONTROL_EOP, /* Generate EOP */
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0, /* read fixed */
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SGDMA_CONTROL_WR_FIXED); /* Generate SOP */
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sgdma_async_write(priv, cdesc);
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/* enqueue the request to the pending transmit queue */
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queue_tx(priv, buffer);
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return 1;
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}
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/* tx_lock held to protect access to queued tx list
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*/
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u32 sgdma_tx_completions(struct altera_tse_private *priv)
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{
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u32 ready = 0;
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if (!sgdma_txbusy(priv) &&
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((csrrd8(priv->tx_dma_desc, sgdma_descroffs(control))
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& SGDMA_CONTROL_HW_OWNED) == 0) &&
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(dequeue_tx(priv))) {
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ready = 1;
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}
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return ready;
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}
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void sgdma_start_rxdma(struct altera_tse_private *priv)
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{
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sgdma_async_read(priv);
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}
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void sgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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{
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queue_rx(priv, rxbuffer);
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}
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/* status is returned on upper 16 bits,
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* length is returned in lower 16 bits
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*/
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u32 sgdma_rx_status(struct altera_tse_private *priv)
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{
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struct sgdma_descrip __iomem *base =
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(struct sgdma_descrip __iomem *)priv->rx_dma_desc;
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struct sgdma_descrip __iomem *desc = NULL;
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struct tse_buffer *rxbuffer = NULL;
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unsigned int rxstatus = 0;
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u32 sts = csrrd32(priv->rx_dma_csr, sgdma_csroffs(status));
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desc = &base[0];
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if (sts & SGDMA_STSREG_EOP) {
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unsigned int pktlength = 0;
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unsigned int pktstatus = 0;
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dma_sync_single_for_cpu(priv->device,
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priv->rxdescphys,
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SGDMA_DESC_LEN,
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DMA_FROM_DEVICE);
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pktlength = csrrd16(desc, sgdma_descroffs(bytes_xferred));
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pktstatus = csrrd8(desc, sgdma_descroffs(status));
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rxstatus = pktstatus & ~SGDMA_STATUS_EOP;
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rxstatus = rxstatus << 16;
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rxstatus |= (pktlength & 0xffff);
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if (rxstatus) {
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csrwr8(0, desc, sgdma_descroffs(status));
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rxbuffer = dequeue_rx(priv);
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if (rxbuffer == NULL)
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netdev_info(priv->dev,
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"sgdma rx and rx queue empty!\n");
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/* Clear control */
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csrwr32(0, priv->rx_dma_csr, sgdma_csroffs(control));
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/* clear status */
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csrwr32(0xf, priv->rx_dma_csr, sgdma_csroffs(status));
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/* kick the rx sgdma after reaping this descriptor */
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sgdma_async_read(priv);
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} else {
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/* If the SGDMA indicated an end of packet on recv,
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* then it's expected that the rxstatus from the
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* descriptor is non-zero - meaning a valid packet
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* with a nonzero length, or an error has been
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* indicated. if not, then all we can do is signal
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* an error and return no packet received. Most likely
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* there is a system design error, or an error in the
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* underlying kernel (cache or cache management problem)
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*/
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netdev_err(priv->dev,
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"SGDMA RX Error Info: %x, %x, %x\n",
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sts, csrrd8(desc, sgdma_descroffs(status)),
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rxstatus);
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}
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} else if (sts == 0) {
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sgdma_async_read(priv);
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}
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return rxstatus;
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}
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/* Private functions */
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static void sgdma_setup_descrip(struct sgdma_descrip __iomem *desc,
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struct sgdma_descrip __iomem *ndesc,
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dma_addr_t ndesc_phys,
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dma_addr_t raddr,
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dma_addr_t waddr,
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u16 length,
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int generate_eop,
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int rfixed,
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int wfixed)
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{
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/* Clear the next descriptor as not owned by hardware */
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u32 ctrl = csrrd8(ndesc, sgdma_descroffs(control));
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ctrl &= ~SGDMA_CONTROL_HW_OWNED;
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csrwr8(ctrl, ndesc, sgdma_descroffs(control));
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ctrl = SGDMA_CONTROL_HW_OWNED;
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ctrl |= generate_eop;
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ctrl |= rfixed;
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ctrl |= wfixed;
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/* Channel is implicitly zero, initialized to 0 by default */
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csrwr32(lower_32_bits(raddr), desc, sgdma_descroffs(raddr));
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csrwr32(lower_32_bits(waddr), desc, sgdma_descroffs(waddr));
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csrwr32(0, desc, sgdma_descroffs(pad1));
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csrwr32(0, desc, sgdma_descroffs(pad2));
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csrwr32(lower_32_bits(ndesc_phys), desc, sgdma_descroffs(next));
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csrwr8(ctrl, desc, sgdma_descroffs(control));
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csrwr8(0, desc, sgdma_descroffs(status));
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csrwr8(0, desc, sgdma_descroffs(wburst));
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csrwr8(0, desc, sgdma_descroffs(rburst));
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csrwr16(length, desc, sgdma_descroffs(bytes));
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csrwr16(0, desc, sgdma_descroffs(bytes_xferred));
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}
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/* If hardware is busy, don't restart async read.
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* if status register is 0 - meaning initial state, restart async read,
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* probably for the first time when populating a receive buffer.
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* If read status indicate not busy and a status, restart the async
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* DMA read.
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*/
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static int sgdma_async_read(struct altera_tse_private *priv)
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{
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struct sgdma_descrip __iomem *descbase =
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(struct sgdma_descrip __iomem *)priv->rx_dma_desc;
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struct sgdma_descrip __iomem *cdesc = &descbase[0];
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struct sgdma_descrip __iomem *ndesc = &descbase[1];
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struct tse_buffer *rxbuffer = NULL;
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if (!sgdma_rxbusy(priv)) {
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rxbuffer = queue_rx_peekhead(priv);
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if (rxbuffer == NULL) {
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netdev_err(priv->dev, "no rx buffers available\n");
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return 0;
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}
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sgdma_setup_descrip(cdesc, /* current descriptor */
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ndesc, /* next descriptor */
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sgdma_rxphysaddr(priv, ndesc),
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0, /* read addr 0 for rx dma */
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rxbuffer->dma_addr, /* write addr for rx dma */
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0, /* read 'til EOP */
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0, /* EOP: NA for rx dma */
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0, /* read fixed: NA for rx dma */
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0); /* SOP: NA for rx DMA */
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dma_sync_single_for_device(priv->device,
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priv->rxdescphys,
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SGDMA_DESC_LEN,
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DMA_TO_DEVICE);
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csrwr32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
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priv->rx_dma_csr,
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sgdma_csroffs(next_descrip));
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csrwr32((priv->rxctrlreg | SGDMA_CTRLREG_START),
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priv->rx_dma_csr,
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sgdma_csroffs(control));
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return 1;
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}
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return 0;
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}
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static int sgdma_async_write(struct altera_tse_private *priv,
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struct sgdma_descrip __iomem *desc)
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{
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if (sgdma_txbusy(priv))
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return 0;
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/* clear control and status */
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csrwr32(0, priv->tx_dma_csr, sgdma_csroffs(control));
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csrwr32(0x1f, priv->tx_dma_csr, sgdma_csroffs(status));
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dma_sync_single_for_device(priv->device, priv->txdescphys,
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SGDMA_DESC_LEN, DMA_TO_DEVICE);
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csrwr32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
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priv->tx_dma_csr,
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sgdma_csroffs(next_descrip));
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csrwr32((priv->txctrlreg | SGDMA_CTRLREG_START),
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priv->tx_dma_csr,
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sgdma_csroffs(control));
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return 1;
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}
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static dma_addr_t
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sgdma_txphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip __iomem *desc)
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{
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dma_addr_t paddr = priv->txdescmem_busaddr;
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uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->tx_dma_desc;
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return (dma_addr_t)((uintptr_t)paddr + offs);
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}
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static dma_addr_t
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sgdma_rxphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip __iomem *desc)
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{
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dma_addr_t paddr = priv->rxdescmem_busaddr;
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uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->rx_dma_desc;
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return (dma_addr_t)((uintptr_t)paddr + offs);
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}
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#define list_remove_head(list, entry, type, member) \
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do { \
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entry = NULL; \
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if (!list_empty(list)) { \
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entry = list_entry((list)->next, type, member); \
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list_del_init(&entry->member); \
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} \
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} while (0)
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#define list_peek_head(list, entry, type, member) \
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do { \
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entry = NULL; \
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if (!list_empty(list)) { \
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entry = list_entry((list)->next, type, member); \
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} \
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} while (0)
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/* adds a tse_buffer to the tail of a tx buffer list.
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static void
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queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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list_add_tail(&buffer->lh, &priv->txlisthd);
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}
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/* adds a tse_buffer to the tail of a rx buffer list
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static void
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queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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list_add_tail(&buffer->lh, &priv->rxlisthd);
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}
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/* dequeues a tse_buffer from the transmit buffer list, otherwise
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* returns NULL if empty.
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static struct tse_buffer *
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dequeue_tx(struct altera_tse_private *priv)
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{
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struct tse_buffer *buffer = NULL;
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list_remove_head(&priv->txlisthd, buffer, struct tse_buffer, lh);
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return buffer;
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}
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/* dequeues a tse_buffer from the receive buffer list, otherwise
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* returns NULL if empty
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static struct tse_buffer *
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dequeue_rx(struct altera_tse_private *priv)
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{
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struct tse_buffer *buffer = NULL;
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list_remove_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
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return buffer;
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}
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/* dequeues a tse_buffer from the receive buffer list, otherwise
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* returns NULL if empty
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list while the
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* head is being examined.
|
|
*/
|
|
static struct tse_buffer *
|
|
queue_rx_peekhead(struct altera_tse_private *priv)
|
|
{
|
|
struct tse_buffer *buffer = NULL;
|
|
list_peek_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
|
|
return buffer;
|
|
}
|
|
|
|
/* check and return rx sgdma status without polling
|
|
*/
|
|
static int sgdma_rxbusy(struct altera_tse_private *priv)
|
|
{
|
|
return csrrd32(priv->rx_dma_csr, sgdma_csroffs(status))
|
|
& SGDMA_STSREG_BUSY;
|
|
}
|
|
|
|
/* waits for the tx sgdma to finish it's current operation, returns 0
|
|
* when it transitions to nonbusy, returns 1 if the operation times out
|
|
*/
|
|
static int sgdma_txbusy(struct altera_tse_private *priv)
|
|
{
|
|
int delay = 0;
|
|
|
|
/* if DMA is busy, wait for current transaction to finish */
|
|
while ((csrrd32(priv->tx_dma_csr, sgdma_csroffs(status))
|
|
& SGDMA_STSREG_BUSY) && (delay++ < 100))
|
|
udelay(1);
|
|
|
|
if (csrrd32(priv->tx_dma_csr, sgdma_csroffs(status))
|
|
& SGDMA_STSREG_BUSY) {
|
|
netdev_err(priv->dev, "timeout waiting for tx dma\n");
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|