362 lines
9.0 KiB
C
362 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2015 Atmel Corporation,
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* Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define GENERATED_MAX_DIV 255
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struct clk_generated {
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struct clk_hw hw;
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struct regmap *regmap;
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struct clk_range range;
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spinlock_t *lock;
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u32 *mux_table;
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u32 id;
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u32 gckdiv;
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const struct clk_pcr_layout *layout;
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struct at91_clk_pms pms;
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u8 parent_id;
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int chg_pid;
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};
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#define to_clk_generated(hw) \
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container_of(hw, struct clk_generated, hw)
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static int clk_generated_set(struct clk_generated *gck, int status)
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{
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unsigned long flags;
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unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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regmap_update_bits(gck->regmap, gck->layout->offset,
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AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
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gck->layout->cmd | enable,
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field_prep(gck->layout->gckcss_mask, gck->parent_id) |
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gck->layout->cmd |
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FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
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enable);
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spin_unlock_irqrestore(gck->lock, flags);
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return 0;
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}
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static int clk_generated_enable(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
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__func__, gck->gckdiv, gck->parent_id);
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clk_generated_set(gck, 1);
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return 0;
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}
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static void clk_generated_disable(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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unsigned long flags;
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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regmap_update_bits(gck->regmap, gck->layout->offset,
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gck->layout->cmd | AT91_PMC_PCR_GCKEN,
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gck->layout->cmd);
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spin_unlock_irqrestore(gck->lock, flags);
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}
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static int clk_generated_is_enabled(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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unsigned long flags;
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unsigned int status;
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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regmap_read(gck->regmap, gck->layout->offset, &status);
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spin_unlock_irqrestore(gck->lock, flags);
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return !!(status & AT91_PMC_PCR_GCKEN);
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}
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static unsigned long
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clk_generated_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
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}
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static void clk_generated_best_diff(struct clk_rate_request *req,
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struct clk_hw *parent,
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unsigned long parent_rate, u32 div,
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int *best_diff, long *best_rate)
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{
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unsigned long tmp_rate;
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int tmp_diff;
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if (!div)
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tmp_rate = parent_rate;
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else
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tmp_rate = parent_rate / div;
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if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
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return;
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tmp_diff = abs(req->rate - tmp_rate);
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if (*best_diff < 0 || *best_diff >= tmp_diff) {
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*best_rate = tmp_rate;
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*best_diff = tmp_diff;
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req->best_parent_rate = parent_rate;
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req->best_parent_hw = parent;
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}
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}
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static int clk_generated_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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struct clk_hw *parent = NULL;
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long best_rate = -EINVAL;
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unsigned long min_rate, parent_rate;
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int best_diff = -1;
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int i;
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u32 div;
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/* do not look for a rate that is outside of our range */
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if (gck->range.max && req->rate > gck->range.max)
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req->rate = gck->range.max;
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if (gck->range.min && req->rate < gck->range.min)
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req->rate = gck->range.min;
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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if (gck->chg_pid == i)
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continue;
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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parent_rate = clk_hw_get_rate(parent);
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min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
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if (!parent_rate ||
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(gck->range.max && min_rate > gck->range.max))
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continue;
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div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
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if (div > GENERATED_MAX_DIV + 1)
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div = GENERATED_MAX_DIV + 1;
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clk_generated_best_diff(req, parent, parent_rate, div,
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&best_diff, &best_rate);
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if (!best_diff)
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break;
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}
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/*
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* The audio_pll rate can be modified, unlike the five others clocks
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* that should never be altered.
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* The audio_pll can technically be used by multiple consumers. However,
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* with the rate locking, the first consumer to enable to clock will be
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* the one definitely setting the rate of the clock.
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* Since audio IPs are most likely to request the same rate, we enforce
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* that the only clks able to modify gck rate are those of audio IPs.
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*/
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if (gck->chg_pid < 0)
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goto end;
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parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
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if (!parent)
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goto end;
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for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
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struct clk_rate_request req_parent;
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clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate * div);
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if (__clk_determine_rate(parent, &req_parent))
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continue;
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clk_generated_best_diff(req, parent, req_parent.rate, div,
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&best_diff, &best_rate);
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if (!best_diff)
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break;
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}
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end:
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pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
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__func__, best_rate,
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__clk_get_name((req->best_parent_hw)->clk),
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req->best_parent_rate);
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if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
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return -EINVAL;
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req->rate = best_rate;
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return 0;
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}
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/* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
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static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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if (index >= clk_hw_get_num_parents(hw))
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return -EINVAL;
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if (gck->mux_table)
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gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
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else
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gck->parent_id = index;
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return 0;
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}
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static u8 clk_generated_get_parent(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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return gck->parent_id;
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}
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/* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
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static int clk_generated_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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u32 div;
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if (!rate)
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return -EINVAL;
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if (gck->range.max && rate > gck->range.max)
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return -EINVAL;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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if (div > GENERATED_MAX_DIV + 1 || !div)
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return -EINVAL;
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gck->gckdiv = div - 1;
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return 0;
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}
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static int clk_generated_save_context(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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gck->pms.status = clk_generated_is_enabled(&gck->hw);
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return 0;
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}
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static void clk_generated_restore_context(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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if (gck->pms.status)
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clk_generated_set(gck, gck->pms.status);
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}
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static const struct clk_ops generated_ops = {
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.enable = clk_generated_enable,
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.disable = clk_generated_disable,
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.is_enabled = clk_generated_is_enabled,
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.recalc_rate = clk_generated_recalc_rate,
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.determine_rate = clk_generated_determine_rate,
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.get_parent = clk_generated_get_parent,
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.set_parent = clk_generated_set_parent,
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.set_rate = clk_generated_set_rate,
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.save_context = clk_generated_save_context,
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.restore_context = clk_generated_restore_context,
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};
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/**
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* clk_generated_startup - Initialize a given clock to its default parent and
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* divisor parameter.
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*
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* @gck: Generated clock to set the startup parameters for.
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*
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* Take parameters from the hardware and update local clock configuration
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* accordingly.
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*/
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static void clk_generated_startup(struct clk_generated *gck)
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{
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u32 tmp;
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unsigned long flags;
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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regmap_read(gck->regmap, gck->layout->offset, &tmp);
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spin_unlock_irqrestore(gck->lock, flags);
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gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
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gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
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}
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struct clk_hw * __init
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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const struct clk_pcr_layout *layout,
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const char *name, const char **parent_names,
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u32 *mux_table, u8 num_parents, u8 id,
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const struct clk_range *range,
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int chg_pid)
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{
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struct clk_generated *gck;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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gck = kzalloc(sizeof(*gck), GFP_KERNEL);
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if (!gck)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &generated_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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if (chg_pid >= 0)
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init.flags |= CLK_SET_RATE_PARENT;
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gck->id = id;
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gck->hw.init = &init;
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gck->regmap = regmap;
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gck->lock = lock;
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gck->range = *range;
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gck->chg_pid = chg_pid;
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gck->layout = layout;
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gck->mux_table = mux_table;
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clk_generated_startup(gck);
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hw = &gck->hw;
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ret = clk_hw_register(NULL, &gck->hw);
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if (ret) {
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kfree(gck);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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