209 lines
6.3 KiB
YAML
209 lines
6.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 Texas Instruments Incorporated
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Texas Instruments J721E Display Subsystem
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maintainers:
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- Jyri Sarha <jsarha@ti.com>
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- Tomi Valkeinen <tomi.valkeinen@ti.com>
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description: |
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The J721E TI Keystone Display SubSystem with four output ports and
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four video planes. There is two full video planes and two "lite
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planes" without scaling support. The video ports can be connected to
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the SoC's DPI pins or to integrated display bridges on the SoC.
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properties:
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compatible:
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const: ti,j721e-dss
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reg:
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items:
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- description: common_m DSS Master common
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- description: common_s0 DSS Shared common 0
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- description: common_s1 DSS Shared common 1
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- description: common_s2 DSS Shared common 2
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- description: VIDL1 light video plane 1
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- description: VIDL2 light video plane 2
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- description: VID1 video plane 1
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- description: VID1 video plane 2
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- description: OVR1 overlay manager for vp1
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- description: OVR2 overlay manager for vp2
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- description: OVR3 overlay manager for vp3
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- description: OVR4 overlay manager for vp4
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- description: VP1 video port 1
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- description: VP2 video port 2
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- description: VP3 video port 3
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- description: VP4 video port 4
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- description: WB Write Back
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reg-names:
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items:
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- const: common_m
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- const: common_s0
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- const: common_s1
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- const: common_s2
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- const: vidl1
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- const: vidl2
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- const: vid1
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- const: vid2
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- const: ovr1
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- const: ovr2
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- const: ovr3
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- const: ovr4
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- const: vp1
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- const: vp2
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- const: vp3
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- const: vp4
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- const: wb
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clocks:
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items:
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- description: fck DSS functional clock
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- description: vp1 Video Port 1 pixel clock
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- description: vp2 Video Port 2 pixel clock
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- description: vp3 Video Port 3 pixel clock
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- description: vp4 Video Port 4 pixel clock
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clock-names:
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items:
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- const: fck
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- const: vp1
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- const: vp2
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- const: vp3
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- const: vp4
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assigned-clocks:
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minItems: 1
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maxItems: 5
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assigned-clock-parents:
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minItems: 1
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maxItems: 5
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interrupts:
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items:
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- description: common_m DSS Master common
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- description: common_s0 DSS Shared common 0
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- description: common_s1 DSS Shared common 1
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- description: common_s2 DSS Shared common 2
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interrupt-names:
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items:
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- const: common_m
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- const: common_s0
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- const: common_s1
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- const: common_s2
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power-domains:
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maxItems: 1
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description: phandle to the associated power domain
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dma-coherent:
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type: boolean
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The output port node form video port 1
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The output port node from video port 2
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The output port node from video port 3
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port@3:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The output port node from video port 4
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max-memory-bandwidth:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Input memory (from main memory to dispc) bandwidth limit in
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bytes per second
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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dss: dss@4a00000 {
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compatible = "ti,j721e-dss";
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reg = <0x04a00000 0x10000>, /* common_m */
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<0x04a10000 0x10000>, /* common_s0*/
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<0x04b00000 0x10000>, /* common_s1*/
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<0x04b10000 0x10000>, /* common_s2*/
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<0x04a20000 0x10000>, /* vidl1 */
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<0x04a30000 0x10000>, /* vidl2 */
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<0x04a50000 0x10000>, /* vid1 */
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<0x04a60000 0x10000>, /* vid2 */
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<0x04a70000 0x10000>, /* ovr1 */
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<0x04a90000 0x10000>, /* ovr2 */
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<0x04ab0000 0x10000>, /* ovr3 */
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<0x04ad0000 0x10000>, /* ovr4 */
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<0x04a80000 0x10000>, /* vp1 */
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<0x04aa0000 0x10000>, /* vp2 */
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<0x04ac0000 0x10000>, /* vp3 */
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<0x04ae0000 0x10000>, /* vp4 */
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<0x04af0000 0x10000>; /* wb */
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reg-names = "common_m", "common_s0",
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"common_s1", "common_s2",
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"vidl1", "vidl2","vid1","vid2",
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"ovr1", "ovr2", "ovr3", "ovr4",
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"vp1", "vp2", "vp3", "vp4",
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"wb";
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clocks = <&k3_clks 152 0>,
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<&k3_clks 152 1>,
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<&k3_clks 152 4>,
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<&k3_clks 152 9>,
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<&k3_clks 152 13>;
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clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common_m",
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"common_s0",
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"common_s1",
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"common_s2";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpi_out_0: endpoint {
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remote-endpoint = <&dp_bridge_input>;
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};
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};
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};
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};
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