223 lines
5.5 KiB
YAML
223 lines
5.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU dt properties for QCM2290 target
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maintainers:
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- Loic Poulain <loic.poulain@linaro.org>
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description: |
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
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and DPU are mentioned for QCM2290 target.
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properties:
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compatible:
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items:
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- const: qcom,qcm2290-mdss
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reg:
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maxItems: 1
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reg-names:
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const: mdss
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AXI clock
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#address-cells": true
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"#size-cells": true
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"#interrupt-cells":
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const: 1
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iommus:
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items:
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
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ranges: true
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interconnects:
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items:
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- description: Interconnect path specifying the port ids for data bus
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interconnect-names:
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const: mdp0-mem
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resets:
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items:
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- description: MDSS_CORE reset
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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description: Node containing the properties of DPU.
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additionalProperties: false
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properties:
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compatible:
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items:
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- const: qcom,qcm2290-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display AXI clock from gcc
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- description: Display AHB clock from dispcc
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- description: Display core clock from dispcc
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- description: Display lut clock from dispcc
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- description: Display vsync clock from dispcc
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clock-names:
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items:
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- const: bus
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- const: iface
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- const: core
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- const: lut
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- const: vsync
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Contains the list of output ports from DPU device. These ports
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connect to interfaces that are external to the DPU hardware,
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such as DSI. Each output port contains an endpoint that
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describes how it is connected to an external interface.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF1 (DSI1)
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required:
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- port@0
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- interrupts
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- power-domains
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- operating-points-v2
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- ports
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required:
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- compatible
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- reg
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- reg-names
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- power-domains
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- clocks
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- interrupts
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- interrupt-controller
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- iommus
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
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#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,qcm2290.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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mdss: mdss@5e00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,qcm2290-mdss";
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reg = <0x05e00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "core";
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
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interconnect-names = "mdp0-mem";
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iommus = <&apps_smmu 0x420 0x2>,
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<&apps_smmu 0x421 0x0>;
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ranges;
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mdss_mdp: display-controller@5e01000 {
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compatible = "qcom,qcm2290-dpu";
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reg = <0x05e01000 0x8f000>,
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<0x05eb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus", "iface", "core", "lut", "vsync";
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmpd QCM2290_VDDCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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};
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...
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