224 lines
		
	
	
		
			5.4 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
			
		
		
	
	
			224 lines
		
	
	
		
			5.4 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU dt properties for MSM8998 target
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maintainers:
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  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
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description: |
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  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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  bindings of MDSS and DPU are mentioned for MSM8998 target.
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properties:
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  compatible:
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    items:
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      - const: qcom,msm8998-mdss
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  reg:
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    maxItems: 1
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  reg-names:
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    const: mdss
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  power-domains:
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    maxItems: 1
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  clocks:
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    items:
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      - description: Display AHB clock
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      - description: Display AXI clock
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      - description: Display core clock
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  clock-names:
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    items:
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      - const: iface
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      - const: bus
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      - const: core
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  interrupts:
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    maxItems: 1
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  interrupt-controller: true
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  "#address-cells": true
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  "#size-cells": true
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  "#interrupt-cells":
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    const: 1
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  iommus:
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    items:
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      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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  ranges: true
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patternProperties:
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  "^display-controller@[0-9a-f]+$":
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    type: object
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    description: Node containing the properties of DPU.
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    additionalProperties: false
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    properties:
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      compatible:
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        items:
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          - const: qcom,msm8998-dpu
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      reg:
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        items:
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          - description: Address offset and size for mdp register set
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          - description: Address offset and size for regdma register set
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          - description: Address offset and size for vbif register set
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          - description: Address offset and size for non-realtime vbif register set
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      reg-names:
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        items:
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          - const: mdp
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          - const: regdma
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          - const: vbif
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          - const: vbif_nrt
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      clocks:
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        items:
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          - description: Display ahb clock
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          - description: Display axi clock
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          - description: Display mem-noc clock
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          - description: Display core clock
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          - description: Display vsync clock
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      clock-names:
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        items:
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          - const: iface
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          - const: bus
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          - const: mnoc
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          - const: core
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          - const: vsync
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      interrupts:
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        maxItems: 1
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      power-domains:
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        maxItems: 1
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      operating-points-v2: true
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      opp-table:
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        type: object
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      ports:
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        $ref: /schemas/graph.yaml#/properties/ports
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        description: |
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          Contains the list of output ports from DPU device. These ports
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          connect to interfaces that are external to the DPU hardware,
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          such as DSI, DP etc. Each output port contains an endpoint that
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          describes how it is connected to an external interface.
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        properties:
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          port@0:
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            $ref: /schemas/graph.yaml#/properties/port
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            description: DPU_INTF1 (DSI1)
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          port@1:
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            $ref: /schemas/graph.yaml#/properties/port
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            description: DPU_INTF2 (DSI2)
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        required:
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          - port@0
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          - port@1
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    required:
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      - compatible
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      - reg
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      - reg-names
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      - clocks
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      - interrupts
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      - power-domains
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      - operating-points-v2
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      - ports
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required:
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  - compatible
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  - reg
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  - reg-names
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  - power-domains
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  - clocks
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  - interrupts
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  - interrupt-controller
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  - iommus
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  - ranges
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additionalProperties: false
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examples:
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  - |
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    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
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    #include <dt-bindings/interrupt-controller/arm-gic.h>
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    #include <dt-bindings/power/qcom-rpmpd.h>
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    mdss: display-subsystem@c900000 {
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        compatible = "qcom,msm8998-mdss";
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        reg = <0x0c900000 0x1000>;
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        reg-names = "mdss";
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        clocks = <&mmcc MDSS_AHB_CLK>,
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                 <&mmcc MDSS_AXI_CLK>,
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                 <&mmcc MDSS_MDP_CLK>;
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        clock-names = "iface", "bus", "core";
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        #address-cells = <1>;
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        #interrupt-cells = <1>;
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        #size-cells = <1>;
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        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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        interrupt-controller;
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        iommus = <&mmss_smmu 0>;
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        power-domains = <&mmcc MDSS_GDSC>;
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        ranges;
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        display-controller@c901000 {
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            compatible = "qcom,msm8998-dpu";
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            reg = <0x0c901000 0x8f000>,
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                  <0x0c9a8e00 0xf0>,
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                  <0x0c9b0000 0x2008>,
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                  <0x0c9b8000 0x1040>;
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            reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
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            clocks = <&mmcc MDSS_AHB_CLK>,
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                     <&mmcc MDSS_AXI_CLK>,
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                     <&mmcc MNOC_AHB_CLK>,
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                     <&mmcc MDSS_MDP_CLK>,
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                     <&mmcc MDSS_VSYNC_CLK>;
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            clock-names = "iface", "bus", "mnoc", "core", "vsync";
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            interrupt-parent = <&mdss>;
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            interrupts = <0>;
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            operating-points-v2 = <&mdp_opp_table>;
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            power-domains = <&rpmpd MSM8998_VDDMX>;
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            ports {
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                #address-cells = <1>;
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                #size-cells = <0>;
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                port@0 {
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                    reg = <0>;
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                    dpu_intf1_out: endpoint {
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                        remote-endpoint = <&dsi0_in>;
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                    };
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                };
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                port@1 {
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                    reg = <1>;
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                    dpu_intf2_out: endpoint {
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                        remote-endpoint = <&dsi1_in>;
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                    };
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                };
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            };
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        };
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    };
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...
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